[WIP] Implement 5-stage pipelined CPU simulator

[Copilot]

• Create directory structure (kernel/cpu/, benchmarks/)
• Implement 5-stage pipelined CPU (pipeline.c/h)
  • Define PipelineStage struct
  • Implement clock cycle simulation
  • Add hazard detection
  • Track cycles and instructions
• Implement single-cycle CPU (single_cycle.c/h)
  • One instruction per cycle model
  • Same interface as pipeline
• Implement direct-mapped cache (cache.c/h in memory/)
  • 256 lines, 32 bytes per block
  • Hit/miss detection
  • Address parsing (tag, index, offset)
• Implement memory bus simulation (bus.c/h in memory/)
  • 64-bit width, 800 MHz
  • Memory access timing
• Implement performance counters (performance.c/h in kernel/cpu/)
  • CPI, MIPS calculation
  • Cache statistics
• Create benchmark (pipeline_vs_single.c in benchmarks/)
  • Execute 20,000 instructions
  • Compare performance
• Update Makefile to build new modules
• Test build and verify functionality
• Run code review and security checks

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