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8390765: [PPC64] AES Crypto intrinsics may access memory beyond the key array #770

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8390765: [PPC64] AES Crypto intrinsics may access memory beyond the key array #770

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22 changes: 22 additions & 0 deletions src/hotspot/cpu/ppc/assembler_ppc.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -544,6 +544,10 @@ class Assembler : public AbstractAssembler {
STXVL_OPCODE = (31u << OPCODE_SHIFT | 397u << 1),
LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
LXVW4X_OPCODE = (31u << OPCODE_SHIFT | 780u << 1),
STXVW4X_OPCODE = (31u << OPCODE_SHIFT | 908u << 1),
LXVB16X_OPCODE = (31u << OPCODE_SHIFT | 876u << 1),
STXVB16X_OPCODE= (31u << OPCODE_SHIFT | 1004u << 1),
MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
MTVSRDD_OPCODE = (31u << OPCODE_SHIFT | 435u << 1),
MTVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 243u << 1),
Expand Down Expand Up @@ -2375,8 +2379,17 @@ class Assembler : public AbstractAssembler {
inline void lxvd2x( VectorSRegister d, Register a, Register b);
inline void stxvd2x( VectorSRegister d, Register a);
inline void stxvd2x( VectorSRegister d, Register a, Register b);
inline void lxvw4x( VectorSRegister d, Register a);
inline void lxvw4x( VectorSRegister d, Register a, Register b);
inline void stxvw4x( VectorSRegister d, Register a);
inline void stxvw4x( VectorSRegister d, Register a, Register b);

// Power9
inline void lxvb16x( VectorSRegister d, Register a);
inline void lxvb16x( VectorSRegister d, Register a, Register b);
inline void stxvb16x( VectorSRegister d, Register a);
inline void stxvb16x( VectorSRegister d, Register a, Register b);

inline void lxv( VectorSRegister d, int si16, Register a);
inline void stxv( VectorSRegister d, int si16, Register a);
inline void lxvx( VectorSRegister d, Register a, Register b);
Expand Down Expand Up @@ -2573,6 +2586,15 @@ class Assembler : public AbstractAssembler {
inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm);
inline void vec_perm(VectorRegister dest, VectorRegister first, VectorRegister second, VectorRegister perm);

// Load/Store unaligned vectors with offs (multiple of 16). Byte versions require vp for Power8 LE.
inline void load_byte_vector_unaligned(VectorRegister dest, int offs, Register base, Register tmp,
VectorRegister vp); // vp should be pre-computed (see generator below)
inline void store_byte_vector_unaligned(VectorRegister val, int offs, Register base, Register tmp,
VectorRegister vp, VectorRegister vtmp = vnoreg); // clobbers val if no vtmp provided
inline void compute_vp_for_byte_vector_unaligned(VectorRegister dest, VectorRegister vtmp);
inline void load_word_vector_unaligned(VectorRegister dest, int offs, Register base, Register tmp);
inline void store_word_vector_unaligned(VectorRegister val, int offs, Register base, Register tmp);

// RegisterOrConstant versions.
// These emitters choose between the versions using two registers and
// those with register and immediate, depending on the content of roc.
Expand Down
110 changes: 110 additions & 0 deletions src/hotspot/cpu/ppc/assembler_ppc.inline.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -864,6 +864,14 @@ inline void Assembler::lxvd2x( VectorSRegister d, Register s1) { e
inline void Assembler::lxvd2x( VectorSRegister d, Register s1, Register s2) { emit_int32( LXVD2X_OPCODE | vsrt(d) | ra0mem(s1) | rb(s2)); }
inline void Assembler::stxvd2x( VectorSRegister d, Register s1) { emit_int32( STXVD2X_OPCODE | vsrs(d) | ra(0) | rb(s1)); }
inline void Assembler::stxvd2x( VectorSRegister d, Register s1, Register s2) { emit_int32( STXVD2X_OPCODE | vsrs(d) | ra0mem(s1) | rb(s2)); }
inline void Assembler::lxvw4x( VectorSRegister d, Register s1) { emit_int32( LXVW4X_OPCODE | vsrt(d) | ra(0) | rb(s1)); }
inline void Assembler::lxvw4x( VectorSRegister d, Register s1, Register s2) { emit_int32( LXVW4X_OPCODE | vsrt(d) | ra0mem(s1) | rb(s2)); }
inline void Assembler::stxvw4x( VectorSRegister d, Register s1) { emit_int32( STXVW4X_OPCODE | vsrs(d) | ra(0) | rb(s1)); }
inline void Assembler::stxvw4x( VectorSRegister d, Register s1, Register s2) { emit_int32( STXVW4X_OPCODE | vsrs(d) | ra0mem(s1) | rb(s2)); }
inline void Assembler::lxvb16x( VectorSRegister d, Register s1) { emit_int32( LXVB16X_OPCODE | vsrt(d) | ra(0) | rb(s1)); }
inline void Assembler::lxvb16x( VectorSRegister d, Register s1, Register s2) { emit_int32( LXVB16X_OPCODE | vsrt(d) | ra0mem(s1) | rb(s2)); }
inline void Assembler::stxvb16x(VectorSRegister d, Register s1) { emit_int32( STXVB16X_OPCODE| vsrs(d) | ra(0) | rb(s1)); }
inline void Assembler::stxvb16x(VectorSRegister d, Register s1, Register s2) { emit_int32( STXVB16X_OPCODE| vsrs(d) | ra0mem(s1) | rb(s2)); }
inline void Assembler::mtvsrd( VectorSRegister d, Register a) { emit_int32( MTVSRD_OPCODE | vsrt(d) | ra(a)); }
inline void Assembler::mtvsrdd( VectorSRegister d, Register a, Register b) { emit_int32( MTVSRDD_OPCODE | vsrt(d) | ra(a) | rb(b)); }
inline void Assembler::mfvsrd( Register d, VectorSRegister a) { emit_int32( MFVSRD_OPCODE | vsrs(a) | ra(d)); }
Expand Down Expand Up @@ -1230,6 +1238,108 @@ inline void Assembler::vec_perm(VectorRegister dest, VectorRegister first, Vecto
#endif
}

inline void Assembler::load_byte_vector_unaligned(VectorRegister dest, int offs, Register base, Register tmp,
VectorRegister vp) {
VectorSRegister vsr = dest->to_vsr();
if (PowerArchitecturePPC64 >= 9) {
#if !defined(VM_LITTLE_ENDIAN)
lxv(vsr, offs, base); // all vector load/store instructions use the same byte order on BE
#else
if (offs == 0) {
lxvb16x(vsr, base);
} else {
li(tmp, offs);
lxvb16x(vsr, base, tmp);
}
#endif
} else { // Power8 only supports very limited instructions
if (offs == 0) {
lxvd2x(vsr, base);
} else {
li(tmp, offs);
lxvd2x(vsr, base, tmp);
}
#if defined(VM_LITTLE_ENDIAN)
// need to swap bytes in both double-words
vperm(dest, dest, dest, vp);
#endif
}
}

inline void Assembler::store_byte_vector_unaligned(VectorRegister val, int offs, Register base, Register tmp,
VectorRegister vp, VectorRegister vtmp) {
VectorSRegister vsr = val->to_vsr();
if (PowerArchitecturePPC64 >= 9) {
#if !defined(VM_LITTLE_ENDIAN)
stxv(vsr, offs, base); // all vector load/store instructions use the same byte order on BE
#else
if (offs == 0) {
stxvb16x(vsr, base);
} else {
li(tmp, offs);
stxvb16x(vsr, base, tmp);
}
#endif
} else { // Power8 only supports very limited instructions
#if defined(VM_LITTLE_ENDIAN)
// need to swap bytes in both double-words
if (vtmp != vnoreg) {
vperm(vtmp, val, val, vp);
vsr = vtmp->to_vsr();
} else {
vperm(val, val, val, vp); // clobbers val!
}
#endif
if (offs == 0) {
stxvd2x(vsr, base);
} else {
li(tmp, offs);
stxvd2x(vsr, base, tmp);
}
}
}

inline void Assembler::compute_vp_for_byte_vector_unaligned(VectorRegister dest, VectorRegister vtmp) {
#if defined(VM_LITTLE_ENDIAN)
if (PowerArchitecturePPC64 < 9) {
li(R0, 0);
vspltisb(vtmp, 7); // vtmp = [7, ..., 7]
lvsl(dest, R0); // dest = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
vxor(dest, dest, vtmp); // dest = [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]
}
#endif
}

inline void Assembler::load_word_vector_unaligned(VectorRegister dest, int offs, Register base, Register tmp) {
VectorSRegister vsr = dest->to_vsr();
#if !defined(VM_LITTLE_ENDIAN)
if (PowerArchitecturePPC64 >= 9) {
lxv(vsr, offs, base); // all vector load/store instructions use the same byte order on BE
} else
#endif
if (offs == 0) {
lxvw4x(vsr, base);
} else {
li(tmp, offs);
lxvw4x(vsr, base, tmp);
}
}

inline void Assembler::store_word_vector_unaligned(VectorRegister val, int offs, Register base, Register tmp) {
VectorSRegister vsr = val->to_vsr();
#if !defined(VM_LITTLE_ENDIAN)
if (PowerArchitecturePPC64 >= 9) {
stxv(vsr, offs, base); // all vector load/store instructions use the same byte order on BE
} else
#endif
if (offs == 0) {
stxvw4x(vsr, base);
} else {
li(tmp, offs);
stxvw4x(vsr, base, tmp);
}
}

inline void Assembler::load_const(Register d, void* x, Register tmp) {
load_const(d, (long)x, tmp);
}
Expand Down
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