usb4: add guarded X1E PHY groundwork and top-port retimer test - #24
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ooaklee wants to merge 13 commits into
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usb4: add guarded X1E PHY groundwork and top-port retimer test#24ooaklee wants to merge 13 commits into
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Some instances of the QMP combo PHY (called USB43DP) feature a third functional sub-block, responsible for USB4/Thunderbolt 3 communication. Compared to the today's state of the binding, one more clock (P2RR2P - PHY-to-Router, Router-to-PHY) needs to be enabled for the PHY to be able to switch to USB4 mode. Allow that for X1E. Also, add a bindings define to let consumers access it. Assisted-by: Claude:sonnet-5 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
There exist OS-accessible USB4 and Thunderbolt PHYs that need specific configuration. Define a new phy_mode for them. Currently, USB4 and TBT3 are defined as submodes, because they're quite distinct, most visibly in the electrical/analog aspects (slightly different frequencies, timings, etc.). This results in a need to make the PHY aware of the actual mode needed (at least in the Qualcomm implementation, but I believe that'll be a general need). Newer versions of TBT are basically supersets of USB4 with higher host-side requirements, so these are not defined. This can always be changed as necessary. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Some Combo PHYs (so far only on SC8280XP, X1E80100 and Glymur), come in a flavor called USB43DP, which as the name implies, features USB4, USB3 and DP signal processing capabilities. In that architecture, USB3 and USB4 PHYs share the same USB_PLL while featuring separate logic spaces. The DP part is roughly the same as on the instances without USB4. The USB4 and USB3/DP operation modes of the PHY are mutually exclusive. Only one USB protocol (and flavor of pipe clock) can be active at a given moment (not to be confused with USB3 not being able to be tunneled as USB4 packets - that of course remains possible). The DP PLL is still used for clocking tunneled DP links. It may be turned off to save power when no tunnels are active, but that's left as a TODO item for now. Due to the nature of USB4, the Type-C handling happens entirely inside the Host Router, and as such the QMPPHY's mux_set() function is nullified for the period when USB4 PHY remains active. This is strictly necessary, as the Host Router driver is going to excercise manual control over the USB4 PHY's power state, which is needed by the suspend and resume flows. Failure to control that synchronously with other parts of the code results in a SoC crash by unlocked access. Because of that, a new struct phy is spawned to expose the USB4 mode, along with a .set_mode callback to allow toggling between USB4 and TBT3 submodes. Thunderbolt 3, having a number of differences vs USB4, requires a couple specific overrides, pertaining to electrical characteristics, which are easily accommodated for. Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Add the offsets and configuration tables to support USB4 and Thunderbolt 3 operation on the USB4-capable PHYs found on Hamoa chips. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
The USB4 part of the QMPPHY requires that one more GCC clock (P2RR2P - PHY-to-Router, Router-to-PHY) is enabled for the PHY to initialize successfully. Describe that. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
The preliminary USB4 mode changes the shared QMP common block while USB and DisplayPort consumers may still hold logical references. Its force path did not propagate all failures, could leave the common resources or pipe clock imbalanced, and could expose a partially switched mode after a failed transition. Track common, regulator, runtime-suspend, and USB power ownership explicitly. Reconfigure mode and orientation as one transaction, stop active USB state before switching, and restore the former common and PHY state when the new configuration fails. Keep the USB4 init and exit paths balanced without programming the PHY twice. Reject physical USB starts in DP-only mode and mode changes while DisplayPort is powered. Serialize runtime PM with the PHY mutex, wrap Type-C callbacks in runtime-PM references, and make cleanup deterministic so an error cannot silently consume a PHY reference. Validated with strict checkpatch, an ARM64 W=1 object build, Denali X1E/X1P DTBs, and independent state-machine review. Runtime PM remains forbidden by default; enabling it manually is outside the v20 production contract. Fixes: d2ddf9d ("phy: qualcomm: qmp-combo: Add preliminary USB4 support") Assisted-by: Codex:gpt-5.6 Assisted-by: OpenCode:omni-route/ds/deepseek-v4-pro
Reserve v20 and later for USB4 and DisplayPort-tunnelling integration so the active v15-v19 pen and touch milestones can evolve independently. Record the public Qualcomm USB43DP PHY v4 backport and its Hamoa clock and electrical data, while keeping both Denali PS8830 retimers behind parade,disable-usb4. The package deliberately claims PHY groundwork only: the Qualcomm host-router implementation and PS8830-to-UC sideband connection are still missing, so direct USB-C DisplayPort Alt Mode remains the supported display path. This split gives package testers and pull-request reviewers an unambiguous version boundary and prevents an experimental USB4 path from being confused with the ongoing pen series. Assisted-by: Codex:gpt-5.6 Assisted-by: OpenCode:omni-route/ds/deepseek-v4-pro
Public experiments have demonstrated Qualcomm router registration, but no published, usable in-tree host-router implementation is enabled by this build. Replace the ambiguous unpublished-router wording with the exact production boundary: v20 provides PHY groundwork, retains the Denali retimer guard, and leaves USB4 and DisplayPort tunnelling gated on the unresolved PS8830-to-UC sideband path. Also describe the existing direct USB-C DisplayPort Alt Mode path as unchanged instead of making a broader support claim that this PHY-only milestone does not revalidate. Assisted-by: Codex:gpt-5.6 Assisted-by: OpenCode:omni-route/ds/deepseek-v4-pro
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Summary
Integrate the public Qualcomm X1E USB43DP PHY v4 groundwork and add a production-safe, explicitly selected Surface Pro 11 top-port retimer qualification path at
7.2.0-jg-0sp11v20.The scoped retimer qualification now passes, but this PR does not claim complete USB4 support. Linux had no active Qualcomm host-router PHY consumer during the test, and no USB4 domain/router, dock USB/Thunderbolt enumeration, or USB3/PCIe/DisplayPort tunnel appeared. Both production Denali PS8830 nodes remain guarded by
parade,disable-usb4.sp11/integration-7.2.x, including the merged pen/touch integration70ddec100fe93dd3b4cProduction safety and experimental selection
parade,disable-usb4on both PS8830 retimers.i2c7, mapped to the physical top port. The bottom-port guard remains.dtb-yand the normaldtbs-list./boot/vmlinuz-*remains guarded./usr/lib/linux-image-<ABI>/sp11-usb4-top-experimental.efi; the package does not install it under/bootor add a GRUB entry.SP11 boots the DTB embedded in the Stubble EFI image, so a loose GRUB
devicetreeline is not an override. The experiment was selected by copying the alternate EFI to a distinct temporary filename and transiently editing only the normal v20 GRUBlinuxpath for one cold boot.Implementation
Public Qualcomm USB43DP PHY v4 series
The provenance-preserving public series remains split into five commits:
076072b40299— binding and USB4 PHY index;b343d089a705— TBT PHY mode and USB4/TBT3 submodes;d2ddf9dce2ef— USB4 PHY instance and lifecycle;c6d1b64af29f— Hamoa USB4/TBT3 electrical data; and8564ca38642c— PHY-to-router clocks.5b5f1d124b7aadds transactional shared-PHY ownership, rollback, and runtime-PM hardening.Retimer qualification increment
75617434c1e6rejects malformed Enter_USB state and adds one-shot PS8830/QMP diagnostics.a57d6d807dbcadds the top-port-only experimental DTS.5321047ea5e2records the experiment in the unchangedsp11v20package version.70ddec100fe9isolates the experiment in its alternate Stubble image.Clean package result
An Ubuntu 26.04
binary-indep binary-qcom-x1ebuild completed from exact head70ddec100fe953712c309067fe2db4d8207facc6withLocal patches: none. All four packages report version7.2.0-jg-0sp11v20; strict verification of the four packages and two provenance manifests passed.Packaged-image inspection confirmed:
.dtbautosections and no experimental model marker;.dtbautowith the exact experimental model;2/1;.linuxpayloads are identical; only embedded DTBs differ;/boot; andExact package and checksum hashes are recorded in companion ADR0068.
Controlled X1E OLED runtime result
The normal v20 control boot had the ordinary OLED model and two live guards. Touch, pen/pressure/barrel button, and a direct USB3 device passed; direct DisplayPort Alt Mode was not retested because suitable hardware was unavailable. A guarded TS4 attach encountered the intended DT policy rejection.
After a cold boot of the transient alternate image, the exact experimental model and one remaining bottom-port guard were verified before attachment. One top-port attach of the matched CalDigit TS4 and bundled 40 Gb/s cable produced:
The first line is emitted only after
ps883x_configure()returns success, so the driver completed its USB4 configuration writes without error. This does not prove the silicon trained a USB4 link or negotiated 40 Gb/s. The second means that a USB4 PHY object existed but had no active host-router PHY consumer at the mux request. It does not establish why initialization was absent or prove that one consumer is the sole remaining blocker.UCSI reported the Type-C/PD partner, but there was no dock USB/PCI enumeration, DRM connector, Thunderbolt device, or USB4 domain. This validates removal of the retimer-side policy rejection for the isolated top-port experiment; it does not validate a USB4 link, working hub, or tunnel.
A subsequent cold boot of the normal unedited v20 image restored the ordinary OLED model and both production guards.
Windows hardware oracle
The reviewed, redacted same-device Windows result proves that the exact TS4, bundled passive 0.8 m 40 Gb/s cable, and physical top port can form a USB4 connection with USB3, PCIe, and DisplayPort tunnels under Windows. It is a matched hardware success oracle, not Linux source or host-router implementation evidence.
Raw Windows and Linux captures remain private. They do not provide a reviewable host-router implementation, MMIO/resource map, firmware/ring protocol, or decoded PS8830 sideband sequence.
Validation
git diff --checkscripts/checkpatch.plW=1buildps883x.koandphy-qcom-qmp-combo.odtbsdtbs-list2/170ddec100fe9Remaining boundary
This remains downstream integration groundwork, not complete in-tree SP11 USB4 support.