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1. fpga-lenet5-accelerator fpga-lenet5-accelerator Public

   FPGA implementation of a quantized LeNet-5 CNN accelerator combining High-Level Synthesis (Vitis HLS) and hand-written RTL (VHDL) for an optimized streaming convolution architecture.

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2. Cordic Cordic Public

   RTL implementation of a fully pipelined CORDIC processor(COrdinate Rotation Digital Computer) in VHDL-2008 with rotation/vectoring modes and automated verification flow

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