feat(KERNEL-QUANT-CIQ-GEMM-ROCM-IQUANT): port IQ4_XS/IQ3_XXS to ROCm

[joral]

Row: KERNEL-QUANT-CIQ-GEMM-ROCM-IQUANT.
Closes #3067. #1940 remains open for the owed formats.

Issue #1940 says src/vt/rocm/ ports zero I-quant formats, so an IQ4_XS or
IQ3_XXS tensor still expands to bf16 on a ROCm keep-quant load instead of
staying compressed. This lands DotIQ4XS and DotIQ3XXS in
rocm_grouped_gemm.hip, adapted from the existing CUDA bodies rather than
freshly ported, on both the plain and grouped/MoE arms, and admits both
dtypes in DeviceKeepQuantSupported's ROCm case. Spec:
.agents/specs/kernel-quant-ciq-gemm-rocm-iquant.md (#2996, merged).

The spec's one named correctness risk is resolved by measurement, not
assumption: CUDA's DotIQ4XS needed non-fused float intrinsics to stay
bit-exact against the oracle, because nvcc's project-wide -ffp-contract=off
never reaches .cu files. HIP already compiles with that flag project-wide,
and a new bit-exact gate over the same real-checkpoint bytes and the same
oracle bits the CUDA gate uses confirms plain arithmetic is sufficient on
this toolchain, so the port carries no workaround CUDA needed.

The contributor reports an end-to-end reload of
the real motivating checkpoint, Nail-Qwen3.6-35B-A3B-MTP-IQ4_XS.gguf
(19.39 GB). It loads, generates coherent tokens, and its calculated weight footprint
(19,333,564,672 bytes, about 18.01 GiB) approximates the on-disk size instead of the ~70 GiB a bf16
expansion would produce — the fix for the host-RAM SIGSEGV this checkpoint
hit on ROCm before this row.

Contributor evidence on the original head, not operator reproduction:
gated on isravale (RX 9060 XT, gfx1200, ROCm 7.2.3) under the GPU file
mutex: test_backend_cross_device 41/42 (the one failure, MoeSiluMul, is
the pre-existing, already-tracked #1954 flake — confirmed unrelated);
test_gguf_keep_quant 52/52; test_gguf_device_fit/test_gguf_device_fit_reach
green; every other ROCm suite green with zero regression on the four
existing k-quant formats.

Owed, named rather than silently dropped: the ROCM-KQUANT-NWARPS-DECODE
re-measurement for these two formats (PENDING, no rocprofv3 profiling
setup staged on this box yet — does not block this row, whose own scope is
coverage and correctness); a WMMA/tensor-core tile for these two formats
(follow-on row KERNEL-QUANT-CIQ-GEMM-ROCM-IQUANT-RDNA4, spec drafted,
depends on this PR merging first); the other six formats named in the same
ROCm refusal message (Q4_0/Q2_K/Q3_K/IQ2_XXS/IQ2_S/MXFP4, tracked by #1940).

Maintainer integration and device verification

Candidate 8a7cda269a7254dc849f6401a990c5f2bae98e36 preserves the
contributor history and reconciles it with main 08a34c3a. It preserves
Tenstorrent admission, K-quant tail arguments, and both independent device
test blocks. A loader test now exercises IQ3_XXS matrix and expert admission
through RouteGgufTensor.

The repair for #3067 compares all four complete device codebooks against
their CPU tables. Static extent checks prevent a partial copy from appearing
complete. No quantization values, arithmetic, or dispatch policy changed.

The operator ran the repaired head under lease
886172b3-9d21-4435-a9db-cbf7b2f5dfb6 on strix:gpu0, gfx1151,
ROCm 7.2.4. All four CTest targets passed:
test_backend_cross_device, test_gguf_keep_quant,
test_gguf_device_fit, and test_gguf_device_fit_reach.
The focused dot and dispatch tests passed 61 assertions. The complete
codebook comparison passed nine assertions.

All eleven independent review mutations failed their intended tests:
six dispatch/codebook/scale mutations and five complete-table-seal mutations.
Every restored source rebuilt and passed its focused tests; zero mutations
survived. The operator also reran the three CPU loader/device-fit suites.
Full host preflight exited 0 with no failed gates, 4/4 changed host translation
units passing, and five disclosed architecture/classification skips.
Explicit path classification, style, and trailer checks supplement that run.

Remaining acceptance gates

The required real-model reload has not been reproduced on the repaired head.
The exact Nail GGUF lacks a recorded repository revision or SHA256 and an
accessible operator location. The contributor's private path is not an
operator-resolved artifact. The checkpoint binding has been requested.

The historical weight-footprint calculation is not measured peak RSS.
Coherent text alone is not a token-ID oracle comparison. Artifact identity,
production reload, token correctness and memory evidence remain pending;
the operator does not claim model acceptance or a speed result from the
four-target device gate. Wider ROCm regression checks and integration with
any newer main also remain to be completed before merge.

FOLLOWING_AGENTS_PROTOCOL

Following-Agents-Protocol: true
AI-Assisted: true
Assisted-by: AGENT:claude-sonnet-5 [Claude Code]
Assisted-by: AGENT:gpt-6 [codex]

[localai-org-maint-bot]

Updated source review at 2280069 (2026-09-09): the requested IQ3_XXS loader regression is present. It calls RouteGgufTensor for matrix and stacked-expert roles and checks keep-quant, opt-out, CPU-reference, and misaligned-width behavior. The diff also adds a snapshot of all four device codebooks and byte comparisons with the CPU tables.

Correction to my earlier documentation feedback: latest main AGENTS.md makes public-document changes depend on their stated triggers; routine code/test edits do not require STATUS/BENCHMARKS updates. That blanket requirement is withdrawn. This head updates the quantization inventory, FEATURES and USAGE.

The remaining merge gate is the real-model reload and token/memory evidence identified in the PR body, bound to an accessible artifact revision or SHA256, plus applicable current-main regression validation. The reported four-target device gate does not establish those model results. I inspected the source changes but did not independently rerun HIP or model gates in this session.