(DICE-1) Midas Venice F32 / Dual Stream Implementation#40

Merged

mrmidi merged 9 commits into

mrmidi:mainfrom

alicankaralar:feat/venice-dual-stream

Jul 9, 2026

Commits on Jul 2, 2026

feat(isoch): per-stream IR/IT context container for multi-stream DICE

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feat(dice): RX de-interleave for multi-stream capture

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fix(isoch): anchor secondary RX slice to master timeline

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fix(isoch): drain every signalled IR context, not just context 0

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feat(dice): per-stream TX wire config — master playback DBS=16

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feat(amdtp): plumb TX sourceChannelOffset for de-interleave (no-op at 0)

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feat(tx): second host playback stream for multi-stream DICE (Venice 17–32)

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fix(isoch): give secondary IT context its own OHCI hardware context

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Commits on Jul 7, 2026

refactor(dice): make Venice RX profile per-stream like TX

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