lan80xx: drive the MCU mailbox + DFU without an INTR_A/B GPIO#12
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It is an adaptation of microchip-ung/sw-mepa#15 |
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please, @Praveen-Kumar-S-Mchp , can you consider this mesa's commit instead ? |
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On boards where no INTR_A/B pin is routed to the host, the MCU mailbox "response ready" interrupt cannot be observed on a GPIO. The 2026.06 code base already tolerates a missing ft_gpio_read callback, but then assumes the host interrupt is always asserted, so every wait degenerates into an unconditional flag-register spin. Introduce lan80xx_mb_host_intr(): return the host-interrupt state from the registered INTR_A/B GPIO callback when one is wired, else poll the SPI-readable MAILBOX_FLAG_REGISTER (HOST_INTR bit). Use it in MB_SendRequest and MB_ReadResponse, and keep DFU's first-packet wait on the assume-asserted + flag-check fallback with an informational trace instead of requiring the callback. With this, the full mailbox protocol and DFU work over SPI alone (e.g. through an SPI mux/proxy), with the GPIO fast path used when available. Signed-off-by: Vincent Jardin <vjardin@free.fr> --- misc information: pushed to: microchip-ung#12 microchip-ung/sw-mepa#15 note: rebased onto v2026.06 (b7fbf51); upstream adopted the callback registration API meanwhile, this refines the no-callback path from assume-asserted to true SPI-flag polling.
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On boards where no INTR_A/B pin is routed to the host, the MCU mailbox "response ready" interrupt cannot be observed on a GPIO. The 2026.06 code base already tolerates a missing ft_gpio_read callback, but then assumes the host interrupt is always asserted, so every wait degenerates into an unconditional flag-register spin. Introduce lan80xx_mb_host_intr(): return the host-interrupt state from the registered INTR_A/B GPIO callback when one is wired, else poll the SPI-readable MAILBOX_FLAG_REGISTER (HOST_INTR bit). Use it in MB_SendRequest and MB_ReadResponse, and keep DFU's first-packet wait on the assume-asserted + flag-check fallback with an informational trace instead of requiring the callback. With this, the full mailbox protocol and DFU work over SPI alone (e.g. through an SPI mux/proxy), with the GPIO fast path used when available. Signed-off-by: Vincent Jardin <vjardin@free.fr> --- misc information: pushed to: microchip-ung#12 microchip-ung/sw-mepa#15 note: rebased onto v2026.06 (b7fbf51); upstream adopted the callback registration API meanwhile, this refines the no-callback path from assume-asserted to true SPI-flag polling. integration (vj_integration_allPR): cherry-picked from: lan80xx-mailbox-dfu-no-intr @ 0b9e38d pull request: microchip-ung#12 pull request: microchip-ung/sw-mepa#15
On boards where no INTR_A/B pin is routed to the host, the MCU mailbox "response ready" interrupt cannot be observed on a GPIO. The 2026.06 code base already tolerates a missing ft_gpio_read callback, but then assumes the host interrupt is always asserted, so every wait degenerates into an unconditional flag-register spin. Introduce lan80xx_mb_host_intr(): return the host-interrupt state from the registered INTR_A/B GPIO callback when one is wired, else poll the SPI-readable MAILBOX_FLAG_REGISTER (HOST_INTR bit). Use it in MB_SendRequest and MB_ReadResponse, and keep DFU's first-packet wait on the assume-asserted + flag-check fallback with an informational trace instead of requiring the callback. With this, the full mailbox protocol and DFU work over SPI alone (e.g. through an SPI mux/proxy), with the GPIO fast path used when available. Signed-off-by: Vincent Jardin <vjardin@free.fr> --- misc information: pushed to: microchip-ung#12 microchip-ung/sw-mepa#15 note: rebased onto v2026.06 (b7fbf51); upstream adopted the callback registration API meanwhile, this refines the no-callback path from assume-asserted to true SPI-flag polling. status: sw-mepa PR microchip-ung#15 closed 2026-07-03 by Microchip (HoratiuVultur): a related patch by Praveen-Kumar-S-Mchp shipped in the mesa v2026.06 release (the ft_gpio_read callback registration this commit refines: it adds SPI-flag polling when no INTR_A/B callback is registered). Review continues on mesa PR microchip-ung#12.
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On boards where no INTR_A/B pin is routed to the host, the MCU mailbox "response ready" interrupt cannot be observed on a GPIO. The 2026.06 code base already tolerates a missing ft_gpio_read callback, but then assumes the host interrupt is always asserted, so every wait degenerates into an unconditional flag-register spin. Introduce lan80xx_mb_host_intr(): return the host-interrupt state from the registered INTR_A/B GPIO callback when one is wired, else poll the SPI-readable MAILBOX_FLAG_REGISTER (HOST_INTR bit). Use it in MB_SendRequest and MB_ReadResponse, and keep DFU's first-packet wait on the assume-asserted + flag-check fallback with an informational trace instead of requiring the callback. With this, the full mailbox protocol and DFU work over SPI alone (e.g. through an SPI mux/proxy), with the GPIO fast path used when available. Signed-off-by: Vincent Jardin <vjardin@free.fr> --- misc information: pushed to: microchip-ung#12 microchip-ung/sw-mepa#15 note: rebased onto v2026.06 (b7fbf51); upstream adopted the callback registration API meanwhile, this refines the no-callback path from assume-asserted to true SPI-flag polling. status: sw-mepa PR microchip-ung#15 closed 2026-07-03 by Microchip (HoratiuVultur): a related patch by Praveen-Kumar-S-Mchp shipped in the mesa v2026.06 release (the ft_gpio_read callback registration this commit refines: it adds SPI-flag polling when no INTR_A/B callback is registered). Review continues on mesa PR microchip-ung#12. integration (vj_integration_allPR): cherry-picked from: lan80xx-mailbox-dfu-no-intr @ 0dff75a pull request: microchip-ung#12 (open) pull request: microchip-ung/sw-mepa#15 (closed 2026-07-03)
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On boards where no INTR_A/B pin is routed to the host, the MCU mailbox "response ready" interrupt cannot be observed on a GPIO. The 2026.06 code base already tolerates a missing ft_gpio_read callback, but then assumes the host interrupt is always asserted, so every wait degenerates into an unconditional flag-register spin. Introduce lan80xx_mb_host_intr(): return the host-interrupt state from the registered INTR_A/B GPIO callback when one is wired, else poll the SPI-readable MAILBOX_FLAG_REGISTER (HOST_INTR bit). Use it in MB_SendRequest and MB_ReadResponse, and keep DFU's first-packet wait on the assume-asserted + flag-check fallback with an informational trace instead of requiring the callback. With this, the full mailbox protocol and DFU work over SPI alone (e.g. through an SPI mux/proxy), with the GPIO fast path used when available. Signed-off-by: Vincent Jardin <vjardin@free.fr> --- misc information: pushed to: microchip-ung#12 microchip-ung/sw-mepa#15 note: rebased onto v2026.06 (b7fbf51); upstream adopted the callback registration API meanwhile, this refines the no-callback path from assume-asserted to true SPI-flag polling. status: sw-mepa PR microchip-ung#15 closed 2026-07-03 by Microchip (HoratiuVultur): a related patch by Praveen-Kumar-S-Mchp shipped in the mesa v2026.06 release (the ft_gpio_read callback registration this commit refines: it adds SPI-flag polling when no INTR_A/B callback is registered). Review continues on mesa PR microchip-ung#12. integration (vj_integration_allPR): cherry-picked from: lan80xx-mailbox-dfu-no-intr @ 0dff75a pull request: microchip-ung#12 (open) pull request: microchip-ung/sw-mepa#15 (closed 2026-07-03)
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On boards where no INTR_A/B pin is routed to the host, the MCU mailbox "response ready" interrupt cannot be observed on a GPIO. The 2026.06 code base already tolerates a missing ft_gpio_read callback, but then assumes the host interrupt is always asserted, so every wait degenerates into an unconditional flag-register spin. Introduce lan80xx_mb_host_intr(): return the host-interrupt state from the registered INTR_A/B GPIO callback when one is wired, else poll the SPI-readable MAILBOX_FLAG_REGISTER (HOST_INTR bit). Use it in MB_SendRequest and MB_ReadResponse, and keep DFU's first-packet wait on the assume-asserted + flag-check fallback with an informational trace instead of requiring the callback. With this, the full mailbox protocol and DFU work over SPI alone (e.g. through an SPI mux/proxy), with the GPIO fast path used when available. Signed-off-by: Vincent Jardin <vjardin@free.fr> --- misc information: pushed to: microchip-ung#12 microchip-ung/sw-mepa#15 note: rebased onto v2026.06 (b7fbf51); upstream adopted the callback registration API meanwhile, this refines the no-callback path from assume-asserted to true SPI-flag polling. status: sw-mepa PR microchip-ung#15 closed 2026-07-03 by Microchip (HoratiuVultur): a related patch by Praveen-Kumar-S-Mchp shipped in the mesa v2026.06 release (the ft_gpio_read callback registration this commit refines: it adds SPI-flag polling when no INTR_A/B callback is registered). Review continues on mesa PR microchip-ung#12. integration (vj_integration_allPR): cherry-picked from: lan80xx-mailbox-dfu-no-intr @ 0dff75a pull request: microchip-ung#12 (open) pull request: microchip-ung/sw-mepa#15 (closed 2026-07-03)
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On boards where no INTR_A/B pin is routed to the host, the MCU mailbox "response ready" interrupt cannot be observed on a GPIO. The 2026.06 code base already tolerates a missing ft_gpio_read callback, but then assumes the host interrupt is always asserted, so every wait degenerates into an unconditional flag-register spin. Introduce lan80xx_mb_host_intr(): return the host-interrupt state from the registered INTR_A/B GPIO callback when one is wired, else poll the SPI-readable MAILBOX_FLAG_REGISTER (HOST_INTR bit). Use it in MB_SendRequest and MB_ReadResponse, and keep DFU's first-packet wait on the assume-asserted + flag-check fallback with an informational trace instead of requiring the callback. With this, the full mailbox protocol and DFU work over SPI alone (e.g. through an SPI mux/proxy), with the GPIO fast path used when available. Signed-off-by: Vincent Jardin <vjardin@free.fr> --- misc information: pushed to: microchip-ung#12 microchip-ung/sw-mepa#15 note: rebased onto v2026.06 (b7fbf51); upstream adopted the callback registration API meanwhile, this refines the no-callback path from assume-asserted to true SPI-flag polling. status: sw-mepa PR microchip-ung#15 closed 2026-07-03 by Microchip (HoratiuVultur): a related patch by Praveen-Kumar-S-Mchp shipped in the mesa v2026.06 release (the ft_gpio_read callback registration this commit refines: it adds SPI-flag polling when no INTR_A/B callback is registered). Review continues on mesa PR microchip-ung#12. integration (vj_integration_allPR): cherry-picked from: lan80xx-mailbox-dfu-no-intr @ 0dff75a pull request: microchip-ung#12 (open) pull request: microchip-ung/sw-mepa#15 (closed 2026-07-03)
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On boards where no INTR_A/B pin is routed to the host, the MCU mailbox "response ready" interrupt cannot be observed on a GPIO. The 2026.06 code base already tolerates a missing ft_gpio_read callback, but then assumes the host interrupt is always asserted, so every wait degenerates into an unconditional flag-register spin. Introduce lan80xx_mb_host_intr(): return the host-interrupt state from the registered INTR_A/B GPIO callback when one is wired, else poll the SPI-readable MAILBOX_FLAG_REGISTER (HOST_INTR bit). Use it in MB_SendRequest and MB_ReadResponse, and keep DFU's first-packet wait on the assume-asserted + flag-check fallback with an informational trace instead of requiring the callback. With this, the full mailbox protocol and DFU work over SPI alone (e.g. through an SPI mux/proxy), with the GPIO fast path used when available. Signed-off-by: Vincent Jardin <vjardin@free.fr> --- misc information: pushed to: microchip-ung#12 microchip-ung/sw-mepa#15 note: rebased onto v2026.06 (b7fbf51); upstream adopted the callback registration API meanwhile, this refines the no-callback path from assume-asserted to true SPI-flag polling. status: sw-mepa PR microchip-ung#15 closed 2026-07-03 by Microchip (HoratiuVultur): a related patch by Praveen-Kumar-S-Mchp shipped in the mesa v2026.06 release (the ft_gpio_read callback registration this commit refines: it adds SPI-flag polling when no INTR_A/B callback is registered). Review continues on mesa PR microchip-ung#12. integration (vj_integration_allPR): cherry-picked from: lan80xx-mailbox-dfu-no-intr @ 0dff75a pull request: microchip-ung#12 (open) pull request: microchip-ung/sw-mepa#15 (closed 2026-07-03)
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On boards where no INTR_A/B pin is routed to the host, the MCU mailbox "response ready" interrupt cannot be observed on a GPIO. The 2026.06 code base already tolerates a missing ft_gpio_read callback, but then assumes the host interrupt is always asserted, so every wait degenerates into an unconditional flag-register spin. Introduce lan80xx_mb_host_intr(): return the host-interrupt state from the registered INTR_A/B GPIO callback when one is wired, else poll the SPI-readable MAILBOX_FLAG_REGISTER (HOST_INTR bit). Use it in MB_SendRequest and MB_ReadResponse, and keep DFU's first-packet wait on the assume-asserted + flag-check fallback with an informational trace instead of requiring the callback. With this, the full mailbox protocol and DFU work over SPI alone (e.g. through an SPI mux/proxy), with the GPIO fast path used when available. Signed-off-by: Vincent Jardin <vjardin@free.fr> --- misc information: pushed to: microchip-ung#12 microchip-ung/sw-mepa#15 note: rebased onto v2026.06 (b7fbf51); upstream adopted the callback registration API meanwhile, this refines the no-callback path from assume-asserted to true SPI-flag polling. status: sw-mepa PR microchip-ung#15 closed 2026-07-03 by Microchip (HoratiuVultur): a related patch by Praveen-Kumar-S-Mchp shipped in the mesa v2026.06 release (the ft_gpio_read callback registration this commit refines: it adds SPI-flag polling when no INTR_A/B callback is registered). Review continues on mesa PR microchip-ung#12. integration (vj_integration_allPR): cherry-picked from: lan80xx-mailbox-dfu-no-intr @ 0dff75a pull request: microchip-ung#12 (open) pull request: microchip-ung/sw-mepa#15 (closed 2026-07-03)
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…t GPIO For the boards where the LAN80xx INTR (MDINT) pin is wired to a host GPIO, the MCU mailbox can wait on the real interrupt instead of polling the flag register over SPI. Let's bind the MEPA gpio callback to a Linux GPIO chardev line with falling-edge events. The INTR line is board-specific, set from $LAN80XX_MDINT, else a built-in default The new CLI command "PHY MCU intr <port_no>" performs the binding. Signed-off-by: Vincent Jardin <vjardin@free.fr> --- misc information: pushed to: microchip-ung#17 complements: microchip-ung#12 (driver-side no-GPIO SPI-flag fallback; independent, reviewable separately) It complements microchip-ung#12 but neither depends on the other.
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On boards where no INTR_A/B pin is routed to the host, the MCU mailbox "response ready" interrupt cannot be observed on a GPIO. The 2026.06 code base already tolerates a missing ft_gpio_read callback, but then assumes the host interrupt is always asserted, so every wait degenerates into an unconditional flag-register spin. Introduce lan80xx_mb_host_intr(): return the host-interrupt state from the registered INTR_A/B GPIO callback when one is wired, else poll the SPI-readable MAILBOX_FLAG_REGISTER (HOST_INTR bit). Use it in MB_SendRequest and MB_ReadResponse, and keep DFU's first-packet wait on the assume-asserted + flag-check fallback with an informational trace instead of requiring the callback. With this, the full mailbox protocol and DFU work over SPI alone (e.g. through an SPI mux/proxy), with the GPIO fast path used when available. Signed-off-by: Vincent Jardin <vjardin@free.fr> --- misc information: pushed to: microchip-ung#12 microchip-ung/sw-mepa#15 note: rebased onto v2026.06 (b7fbf51); upstream adopted the callback registration API meanwhile, this refines the no-callback path from assume-asserted to true SPI-flag polling. status: sw-mepa PR microchip-ung#15 closed 2026-07-03 by Microchip (HoratiuVultur): a related patch by Praveen-Kumar-S-Mchp shipped in the mesa v2026.06 release (the ft_gpio_read callback registration this commit refines: it adds SPI-flag polling when no INTR_A/B callback is registered). Review continues on mesa PR microchip-ung#12. integration (vj_integration_allPR): cherry-picked from: lan80xx-mailbox-dfu-no-intr @ 0dff75a pull request: microchip-ung#12 (open) pull request: microchip-ung/sw-mepa#15 (closed 2026-07-03)
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…t GPIO For the boards where the LAN80xx INTR (MDINT) pin is wired to a host GPIO, the MCU mailbox can wait on the real interrupt instead of polling the flag register over SPI. Let's bind the MEPA gpio callback to a Linux GPIO chardev line with falling-edge events. The INTR line is board-specific, set from $LAN80XX_MDINT, else a built-in default The new CLI command "PHY MCU intr <port_no>" performs the binding. Signed-off-by: Vincent Jardin <vjardin@free.fr> --- misc information: pushed to: microchip-ung#17 complements: microchip-ung#12 (driver-side no-GPIO SPI-flag fallback; independent, reviewable separately) It complements microchip-ung#12 but neither depends on the other. integration (vj_integration_allPR): cherry-picked from: vj_shared_phy_only @ 79314df pull request: microchip-ung#17 (open)
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The mailbox handshake (MB_SendRequest/MB_ReadResponse) and the DFU firmware update gated on a registered ft_gpio_read callback that reads the INTR_A/B pin. On boards where that pin is not routed to a readable host GPIO and there is no MESA switch (e.g. a LAN80xx hung directly off an SoC over SPI in PHY-only mode) no callback is registered, so the mailbox and DFU aborted with "INTR_A/B callback not registered!".
Add lan80xx_mb_host_intr(): when no callback is registered, poll the host-interrupt condition over SPI from MAILBOX_FLAG_REGISTER bit1 (MAILBOX_HOST_INTR_MASK). The same flag the mailbox code re-reads immediately after the gate. Fall back to the registered callback whenever one is present, so EDSx behaviour is unchanged. Use it in MB_SendRequest, MB_ReadResponse and the DFU first-packet wait, and stop aborting DFU when no callback is registered.