[rtl] RRAM Earlgrey integration#30420
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Thanks @gautschimi for the PR. I have reviewed the last three commits and have only added a few minor comments, see below. This LGTM.
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| .rma_req_i(lc_ctrl_lc_nvm_rma_req), | ||
| .rma_ack_o(), | ||
| .rma_seed_i(lc_ctrl_lc_nvm_rma_seed), | ||
| .pwrmgr_o(), | ||
| .keymgr_o(), |
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I guess these open ones will be connected in future PRs? Does the rma protocol work without the ack connected?
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This will get connected in a future PR. In this PR the RMA is still connected to the flash
| .rram_macro_o(rram_ctrl_rram_macro_rsp), | ||
| .lc_nvm_debug_en_i(lc_ctrl_lc_nvm_debug_en), | ||
| .obs_ctrl_i(ast_obs_ctrl), | ||
| .rram_obs_o(), |
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Is this to be connected to AST?
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this is empty at the moment. But it will be used in the future and connected to the AST.
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This commit adds the plug between rram_ctrl and otp_ctrl and will replace otp_macro. It converts otp_ctrl transactions to rram read/write operations. The following operations are supported: - Read, ReadRaw - Write, WriteRaw - Init - Zeroize All values are protected with an additional integrity check value that must match (except for ReadRaw/WriteRaw) Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
The requests from otp_ctrl to rram_ctrl come from the otp_clk domain (clk_io4) and need to be synchronized to the main clock domain (system clock). Two FIFOs (prim_fifo_async_simple) have been added for the request and response path. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
And fix remaining issues in rram_ctrl_otp and top. rram_ctrl_otp required a waifer for FOR_LOOP_BOUNDS, VAR_INDEX_RANGE, LOOP_VAR_OP. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
After manufacturing the RRAM is unprogrammed and OTP read commands will result in garbage and integrity mismatches if the read path tries to remove the address infection. Addr-infection has been disabled for the full OTP region. Integrity is guaranteed with the separate integrity word stored in the integrity page. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
RRAM write operations are less protected than read operations. Therefore, every OTP write is verified with a subsequent read-back. If the readback does not match the original data, an alert is created. (same behaviour as for an OTP read with integrity) Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
This commit adds rram_ctrl + rram_macro and connects them to the bus system. The RRAM can already be used for read/write operations through the controller and host port. Software binaries are still mapped to the flash macro, and otp_ctrl is not yet connected to rram_ctrl. No functional change so far as RRAM is not yet used in any testcase (except for chip level csr_rw test). Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
This commit is to be squashed into the previous one before merge. It contains all autogen changes that were generated with `make -C hw` Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
Align all security countermeasures in sec_cm_testplan, hjson and RTL Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
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This bkdr util is required to preload the RRAM or to examine certain memory location during tests. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
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As per RFC , Earlgrey will be extended with support for RRAM based non-volatile memory.
This 1st integration PR adds the moduls
rram_ctrlandrram_macroto earlgrey.A few remarks:
This PR is based on #30412
The diff of all commits of this PR can be found here:
https://github.com/lowRISC/opentitan/pull/30420/changes/4ea162e0f59e2650a3d141ead1929208ccf48103..ebb62ca9760b9684d496dcbe52d1f1fb70ca96e7
The last 3 commits are relevant for this PR:
Temporary size reduction of the RRAM to 1MB. This commit was intended to support bitstream build on CW310, but it introduces lint issues.