lowRISC · martin-velay · Jun 16, 2026 · Jul 17, 2026 · Jul 20, 2026
diff --git a/hw/top_chip/ip_autogen/alert_handler/dv/alert_handler_sim_cfg.hjson b/hw/top_chip/ip_autogen/alert_handler/dv/alert_handler_sim_cfg.hjson
@@ -40,7 +40,7 @@
              "sec_cm_prim_onehot_check_bind"]
 
   // Default iterations for all tests - each test entry can override this.
-  reseed: 50
+  reseed: 10
 
   overrides: [
     {
@@ -72,45 +72,53 @@
     {
       name: alert_handler_random_classes
       uvm_test_seq: alert_handler_random_classes_vseq
+      reseed: 50
     }
 
     {
       name: alert_handler_esc_intr_timeout
       uvm_test_seq: alert_handler_esc_intr_timeout_vseq
+      reseed: 50
     }
 
     {
       name: alert_handler_esc_alert_accum
       uvm_test_seq: alert_handler_esc_alert_accum_vseq
+      reseed: 25
     }
 
     {
       name: alert_handler_sig_int_fail
       uvm_test_seq: alert_handler_sig_int_fail_vseq
+      reseed: 50
     }
 
     {
       name: alert_handler_entropy
       uvm_test_seq: alert_handler_entropy_vseq
       run_opts: ["+test_timeout_ns=1_000_000_000"]
+      reseed: 25
     }
 
     {
       name: alert_handler_ping_timeout
       uvm_test_seq: alert_handler_ping_timeout_vseq
       run_opts: ["+test_timeout_ns=1_000_000_000"]
+      reseed: 50
     }
 
     {
       name: alert_handler_lpg
       uvm_test_seq: alert_handler_lpg_vseq
       run_opts: ["+test_timeout_ns=1_000_000_000"]
+      reseed: 50
     }
 
     {
       name: alert_handler_lpg_stub_clk
       uvm_test_seq: alert_handler_lpg_stub_clk_vseq
       run_opts: ["+test_timeout_ns=1_000_000_000"]
+      reseed: 50
     }
 
     {
@@ -125,6 +133,7 @@
     {
       name: alert_handler_stress_all
       run_opts: ["+test_timeout_ns=15_000_000_000"]
+      reseed: 50
     }
 
     {

diff --git a/hw/top_chip/ip_autogen/alert_handler/dv/env/alert_handler_env.core b/hw/top_chip/ip_autogen/alert_handler/dv/env/alert_handler_env.core
@@ -51,4 +51,4 @@ targets:
     filesets:
       - files_dv
     generate:
-      - ral
+      - "!chip_level ? (ral)"
diff --git a/hw/top_chip/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson b/hw/top_chip/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson
@@ -42,7 +42,7 @@
              "sec_cm_prim_onehot_check_bind"]
 
   // Default iterations for all tests - each test entry can override this.
-  reseed: 50
+  reseed: 10
 
   // CLKMGR exclusion files.
   vcs_cov_excl_files: ["{self_dir}/cov/clkmgr_cov_manual_excl.el",

diff --git a/hw/top_chip/ip_autogen/clkmgr/dv/env/clkmgr_env.core b/hw/top_chip/ip_autogen/clkmgr/dv/env/clkmgr_env.core
@@ -47,4 +47,4 @@ targets:
     filesets:
       - files_dv
     generate:
-      - ral
+      - "!chip_level ? (ral)"
diff --git a/hw/top_chip/ip_autogen/gpio/dv/env/gpio_env.core b/hw/top_chip/ip_autogen/gpio/dv/env/gpio_env.core
@@ -45,4 +45,4 @@ targets:
     filesets:
       - files_dv
     generate:
-      - ral
+      - "!chip_level ? (ral)"
diff --git a/hw/top_chip/ip_autogen/gpio/dv/gpio_sim_cfg.hjson b/hw/top_chip/ip_autogen/gpio/dv/gpio_sim_cfg.hjson
@@ -39,7 +39,7 @@
   sim_tops: ["gpio_bind", "sec_cm_prim_onehot_check_bind"]
 
   // Default iterations for all tests - each test entry can override this.
-  reseed: 50
+  reseed: 10
 
   // Default UVM test and seq class name.
   uvm_test: gpio_base_test

diff --git a/hw/top_chip/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core b/hw/top_chip/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core
@@ -55,4 +55,4 @@ targets:
     filesets:
       - files_dv
     generate:
-      - ral
+      - "!chip_level ? (ral)"
diff --git a/hw/top_chip/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_glitch_vseq.sv b/hw/top_chip/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_glitch_vseq.sv
@@ -30,11 +30,11 @@ class pwrmgr_glitch_vseq extends pwrmgr_base_vseq;
       cfg.clk_rst_vif.wait_clks(cycles_before_reset);
 
       `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateResetPrep &&
-                        cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx] == 1);, $sformatf(
-                   "checker timeout : fast_state %s, pwr_rst_req 0x%x",
-                   cfg.pwrmgr_vif.fast_state.name,
-                   cfg.pwrmgr_vif.pwr_rst_req.rstreqs
-                   ), 10000)
+                        cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx] == 1);,
+                   $sformatf("checker timeout : fast_state %s, pwr_rst_req 0x%x",
+                             cfg.pwrmgr_vif.fast_state.name,
+                             cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]),
+                   10000)
 
       dut_init();
     end

diff --git a/hw/top_chip/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv b/hw/top_chip/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv
@@ -11,9 +11,6 @@ class pwrmgr_repeat_wakeup_reset_vseq extends pwrmgr_wakeup_reset_vseq;
 
   bit [lc_ctrl_pkg::TxWidth-1:0] bad_lc_tx;
 
-  int cycles_from_reset;
-  int micros_to_release;
-
   bit super_sequence_done;
 
   task body();
@@ -27,38 +24,58 @@ class pwrmgr_repeat_wakeup_reset_vseq extends pwrmgr_wakeup_reset_vseq;
         super.body();
         super_sequence_done = 1;
       end
-      drv_stim(mubi_mode);
+      drv_stim();
     join
   endtask : body
 
-  task drv_stim(pwrmgr_mubi_e mubi_mode);
-    if (mubi_mode == PwrmgrMubiLcCtrl) drv_lc_ctrl();
-  endtask : drv_stim
-
-  task drv_lc_ctrl();
-    int delay;
-
-    `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(cycles_from_reset, cycles_from_reset inside {[2 : 8]};)
-    `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(micros_to_release, micros_to_release inside {[2 : 4]};)
+  task drv_stim();
+    int unsigned cycles_from_reset = $urandom_range(2, 8);
+    int unsigned micros_to_release = $urandom_range(2, 4);
 
     repeat (50) begin : repeat_50
       wait(cfg.esc_clk_rst_vif.rst_n);
       cfg.clk_rst_vif.wait_clks(cycles_from_reset);
-      if (super_sequence_done) begin
-        `uvm_info(`gfn, "Break from drv_lc_ctrl", UVM_MEDIUM)
-        break;
-      end
-      `uvm_info(`gfn, "Injection to lc_hw_debug_en", UVM_MEDIUM)
-      cfg.pwrmgr_vif.lc_hw_debug_en = get_rand_lc_tx_val(
-          .t_weight(1), .f_weight(1), .other_weight(2)
-      );
+      if (super_sequence_done) break;
+
+      drive_inputs(1);
       #(micros_to_release * 1us);
-      `uvm_info(`gfn, "Injection to lc_dft_en", UVM_MEDIUM)
       if (super_sequence_done) break;
-      cfg.pwrmgr_vif.lc_dft_en = get_rand_lc_tx_val(.t_weight(1), .f_weight(1), .other_weight(2));
+
+      drive_inputs(0);
       #(micros_to_release * 1us);
     end : repeat_50
-    `uvm_info(`gfn, "ended drv_lc_ctrl", UVM_MEDIUM)
-  endtask : drv_lc_ctrl
+    `uvm_info(`gfn, "ended drv_stim", UVM_MEDIUM)
+  endtask : drv_stim
+
+  task drive_inputs(bit phase0);
+    case (mubi_mode)
+      PwrmgrMubiLcCtrl:  drive_lc_ctrl_inputs(phase0);
+      PwrmgrMubiRomCtrl: drive_rom_ctrl_inputs(phase0);
+      default: `uvm_fatal(get_full_name(), $sformatf("Unknown mubi_mode: %s", mubi_mode.name()))
+    endcase
+  endtask : drive_inputs
+
+  task drive_rom_ctrl_inputs(bit phase0);
+    if (phase0) begin
+      for (int r = 0; r < NumRomInputs; r++) begin
+        mubi4_t rand_done = get_rand_mubi4_val(.t_weight(1), .f_weight(1), .other_weight(2));
+        mubi4_t rand_good = get_rand_mubi4_val(.t_weight(1), .f_weight(1), .other_weight(2));
+        `uvm_info(`gfn, $sformatf("Injection to rom_ctrl[%0d]", r), UVM_MEDIUM)
+        cfg.pwrmgr_vif.update_rom_ctrl('{done: rand_done, good: rand_good}, r);
+      end
+    end else begin
+      update_roms_response(.done(MuBi4True), .good(MuBi4True));
+    end
+  endtask : drive_rom_ctrl_inputs
+
+  task drive_lc_ctrl_inputs(bit phase0);
+    if (phase0) begin
+      cfg.pwrmgr_vif.lc_hw_debug_en = get_rand_lc_tx_val(.t_weight(1),
+                                                         .f_weight(1),
+                                                         .other_weight(2));
+    end else begin
+      cfg.pwrmgr_vif.lc_dft_en = get_rand_lc_tx_val(.t_weight(1), .f_weight(1), .other_weight(2));
+    end
+  endtask : drive_lc_ctrl_inputs
 
 endclass : pwrmgr_repeat_wakeup_reset_vseq
diff --git a/hw/top_chip/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson b/hw/top_chip/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson
@@ -51,7 +51,7 @@
              "sec_cm_prim_onehot_check_bind"]
 
   // Default iterations for all tests - each test entry can override this.
-  reseed: 50
+  reseed: 10
 
   // Default UVM test and seq class name.
   uvm_test: pwrmgr_base_test
@@ -87,6 +87,11 @@
       uvm_test_seq: pwrmgr_wakeup_reset_vseq
       run_opts: ["+test_timeout_ns=1000000"]
     }
+    {
+      name: pwrmgr_repeat_wakeup_reset
+      uvm_test_seq: pwrmgr_repeat_wakeup_reset_vseq
+      run_opts: ["+test_timeout_ns=4000000", "+pwrmgr_mubi_mode=PwrmgrMubiRomCtrl"]
+    }
     {
       name: pwrmgr_aborted_low_power
       uvm_test_seq: pwrmgr_aborted_low_power_vseq

diff --git a/hw/top_chip/ip_autogen/rstmgr/dv/env/rstmgr_env.core b/hw/top_chip/ip_autogen/rstmgr/dv/env/rstmgr_env.core
@@ -52,4 +52,4 @@ targets:
       - files_dv
       - files_rtl
     generate:
-      - ral
+      - "!chip_level ? (ral)"
diff --git a/hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson b/hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson
@@ -54,7 +54,7 @@
 	     "sec_cm_prim_onehot_check_bind"]
 
   // Default iterations for all tests - each test entry can override this.
-  reseed: 50
+  reseed: 5
 
   // Default UVM test and seq class name.
   uvm_test: rstmgr_base_test
@@ -92,6 +92,7 @@
     {
       name: rstmgr_leaf_rst_cnsty
       uvm_test_seq: rstmgr_leaf_rst_cnsty_vseq
+      reseed: 25
     }
     {
       name: rstmgr_leaf_rst_shadow_attack

diff --git a/hw/top_chip/tmp_sim_cfg/rv_dm_base_sim_cfg.hjson b/hw/top_chip/tmp_sim_cfg/rv_dm_base_sim_cfg.hjson
@@ -83,7 +83,6 @@
       build_mode: "cover_reg_top"
       run_opts: ["+csr_aliasing"]
       en_run_modes: ["csr_tests_mode"]
-      reseed: 5
       run_opts: ["+test_timeout_ns=100_000_000"]
     }
     {

diff --git a/hw/vendor/lowrisc_ip.vendor.hjson b/hw/vendor/lowrisc_ip.vendor.hjson
@@ -1,6 +1,12 @@
 // Copyright lowRISC contributors.
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
+//
+// DD/RTL half of the lowRISC vendoring split. Shares its target_dir
+// ("lowrisc_ip") with hw/vendor/lowrisc_ip_dv.vendor.hjson (the DV half).
+// Run this DD vendor before the DV vendor: this run deletes each ip/<block>
+// directory (including its dv/ subdir) before re-importing. See the DV config
+// header for details.
 {
   name: "lowrisc_ip",
   target_dir: "lowrisc_ip",
@@ -34,7 +40,7 @@
     {from: "hw/ip/lc_ctrl",      to: "ip/lc_ctrl"}, // Dependency of crossbar and power manager.
     {from: "hw/ip/rom_ctrl",     to: "ip/rom_ctrl", patch_dir: "rom_ctrl"}, // Read-only memory.
     {from: "hw/ip/rv_core_ibex", to: "ip/rv_core_pkg", patch_dir: "rv_core_pkg"}, // RISC-V core package.
-    {from: "hw/ip/rv_timer",     to: "ip/rv_timer", patch_dir: "rv_timer"}, // Timer.
+    {from: "hw/ip/rv_timer",     to: "ip/rv_timer"}, // Timer.
     {from: "hw/ip/spi_device",   to: "ip/spi_device", patch_dir: "spi_device"}, // SPI device.
     {from: "hw/ip/spi_host",     to: "ip/spi_host", patch_dir: "spi_host"}, // SPI host.
     {from: "hw/ip/tlul",         to: "ip/tlul", patch_dir: "tlul"}, // Memory bus.
@@ -55,23 +61,11 @@
 
     // Lint.
     {from: "hw/lint", to: "lint", patch_dir: "lint"},
-
-    // Simulation.
-    {from: "hw/dv/dpi/gpiodpi",           to: "dv/dpi/gpiodpi", patch_dir: "gpiodpi"},
-    {from: "hw/dv/dpi/spidpi",            to: "dv/dpi/spidpi"},
-    {from: "hw/dv/dpi/uartdpi",           to: "dv/dpi/uartdpi"},
-    {from: "hw/dv/dpi/jtagdpi",           to: "dv/dpi/jtagdpi"},
-    {from: "hw/dv/dpi/common/tcp_server", to: "dv/dpi/common/tcp_server"},
-    {from: "hw/dv/sv",                    to: "dv/sv", patch_dir: "dv_sv"},
-    {from: "hw/dv/verilator",             to: "dv/verilator", patch_dir: "dv_verilator"},
-
-    // Verification.
-    {from: "hw/dv/tools",       to: "dv/tools",     patch_dir: "dv_tools"},
-    {from: "hw/formal/tools",   to: "formal/tools", patch_dir: "formal_tools"},
   ],
 
   exclude_from_upstream: [
-    "*/BUILD",
-    "hw/dv/tools/vcs",
+    "**/BUILD",
+    "hw/ip/*/dv",
+    "hw/ip_templates/*/dv",
   ],
 }
diff --git a/hw/vendor/lowrisc_ip/dv/sv/alert_esc_agent/alert_esc_agent.sv b/hw/vendor/lowrisc_ip/dv/sv/alert_esc_agent/alert_esc_agent.sv
@@ -5,9 +5,9 @@
 // ---------------------------------------------
 // Alert agent
 // ---------------------------------------------
-class alert_esc_agent extends dv_base_agent#(
+class alert_esc_agent extends dv_reactive_agent #(
     .CFG_T           (alert_esc_agent_cfg),
-    .DRIVER_T        (dv_base_driver#(alert_esc_seq_item, alert_esc_agent_cfg)),
+    .DRIVER_T        (dv_base_driver #(alert_esc_seq_item, alert_esc_agent_cfg)),
     .SEQUENCER_T     (alert_esc_sequencer),
     .MONITOR_T       (alert_esc_base_monitor),
     .COV_T           (alert_esc_agent_cov)

diff --git a/hw/vendor/lowrisc_ip/dv/sv/alert_esc_agent/alert_esc_agent_cfg.sv b/hw/vendor/lowrisc_ip/dv/sv/alert_esc_agent/alert_esc_agent_cfg.sv
@@ -6,7 +6,7 @@
 // ---------------------------------------------
 // Configuration class for Alert agent
 // ---------------------------------------------
-class alert_esc_agent_cfg extends dv_base_agent_cfg;
+class alert_esc_agent_cfg extends dv_reactive_agent_cfg;
   virtual alert_esc_if vif;
   virtual alert_esc_probe_if probe_vif;
   bit is_alert        = 1;

diff --git a/hw/vendor/lowrisc_ip/dv/sv/alert_esc_agent/alert_esc_base_monitor.sv b/hw/vendor/lowrisc_ip/dv/sv/alert_esc_agent/alert_esc_base_monitor.sv
@@ -5,7 +5,7 @@
 
 // A base class for monitors that track alert/escalation items and watch an alert_esc_if.
 
-class alert_esc_base_monitor extends dv_base_monitor #(
+class alert_esc_base_monitor extends dv_reactive_monitor #(
   .ITEM_T(alert_esc_seq_item),
   .CFG_T (alert_esc_agent_cfg),
   .COV_T (alert_esc_agent_cov)

diff --git a/hw/vendor/lowrisc_ip/dv/sv/alert_esc_agent/alert_esc_sequencer.sv b/hw/vendor/lowrisc_ip/dv/sv/alert_esc_agent/alert_esc_sequencer.sv
@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-class alert_esc_sequencer extends dv_base_sequencer#(alert_esc_seq_item, alert_esc_agent_cfg);
+class alert_esc_sequencer extends dv_reactive_sequencer #(alert_esc_seq_item, alert_esc_agent_cfg);
   `uvm_component_utils(alert_esc_sequencer)
 
   extern function new (string name, uvm_component parent);

diff --git a/hw/vendor/lowrisc_ip/dv/sv/cip_lib/cip_base_env_cfg.sv b/hw/vendor/lowrisc_ip/dv/sv/cip_lib/cip_base_env_cfg.sv
@@ -130,8 +130,19 @@ class cip_base_env_cfg #(type RAL_T = dv_base_reg_block) extends dv_base_env_cfg
 
   `uvm_object_new
 
+  // Initialize the register models in the environment
+  //
+  // This works by calling initialize_ral (implemented in dv_base_env_cfg) after ral_model_names has
+  // been initialised. To add a new RAL model, a subclass should extend cip_base_env_cfg::initialize
+  // with a function that adds the model's name to ral_model_names before calling
+  // super.initialize().
   virtual function void initialize();
-    super.initialize();
+    // Initialize the register models themselves. This uses initialize_ral, which is implemented in
+    // dv_base_env_cfg.
+    initialize_ral(bus_params_pkg::BUS_AW,
+                   bus_params_pkg::BUS_DW,
+                   bus_params_pkg::BUS_DBW);
+
     // Create downstream agent cfg objects.
     foreach (ral_model_names[i]) begin
       string ral_name = ral_model_names[i];

diff --git a/hw/vendor/lowrisc_ip/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv b/hw/vendor/lowrisc_ip/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv
@@ -360,9 +360,9 @@ class cip_base_vseq #(
   //   reset_delay_bound  Each time the sequence runs, this task will wait a random amount of time
   //                      before it starts waiting for an opportune time to inject the reset. This
   //                      is the upper bound on that wait.
-  extern protected task run_seq_with_rand_reset_vseq(uvm_sequence seq,
-                                                     int          num_times,
-                                                     uint         reset_delay_bound);
+  extern protected virtual task run_seq_with_rand_reset_vseq(uvm_sequence seq,
+                                                             int          num_times,
+                                                             uint         reset_delay_bound);
 
   // If cfg.can_reset_with_csr_accesses is false, wait_to_issue_reset() will try to wait for a time
   // with no CSR accesses before it injects the reset. The value returned by this function is an