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Add support for assign statement. #2

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989be38
Add support for assign statement.
twweeb May 19, 2021
1ce7853
Add some ISCAS85 benchmarks, and its locked circuits using xor, lut, …
twweeb May 19, 2021
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19 changes: 19 additions & 0 deletions benchmarks/c17/c17.v
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module c17 (N1,N2,N3,N6,N7,N22,N23);

input N1,N2,N3,N6,N7;

output N22,N23;

wire N10,N11,N16,N19;

nand NAND2_1 (N10, N1, N3);
nand NAND2_2 (N11, N3, N6);
nand NAND2_3 (N16, N2, N11);
nand NAND2_4 (N19, N11, N7);
nand NAND2_5 (N22, N10, N16);
nand NAND2_6 (N23, N16, N19);

endmodule



44 changes: 44 additions & 0 deletions benchmarks/c17/c17_aor_8bit.v
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// Verilog File
module c17_aor_8bit.bench (N1,N2,N3,N6,N7,keyinput0,keyinput1,keyinput2,keyinput3,
keyinput4,keyinput5,keyinput6,keyinput7,N22,N23);

input N1,N2,N3,N6,N7,keyinput0,keyinput1,keyinput2,keyinput3,
keyinput4,keyinput5,keyinput6,keyinput7;


output N22, N23;

wire n14, xenc3, xenc5, iw_1, iw_2, iw_3, n12, iw_4, iw_5,
n13, iw_6, xenc2, xenc0, n15, iw_9, n16, n17, n18, n19,
n20, xenc1, iw_0, xenc7, xenc6, iw_7, iw_8, xenc4;

not g0(xenc3, n14);
and g1(N23, xenc5, iw_1);
and g2(n12, iw_2, iw_3);
and g3(n13, iw_4, iw_5);
and g4(n14, iw_6, xenc2);
and g5(n15, xenc5, xenc0);
and g6(n16, iw_2, iw_9);
not g7(n17, N3);
not g8(n18, N1);
not g9(n19, N2);
not g10(n20, N6);
not g11(iw_0, xenc1);
not g12(iw_1, xenc7);
not g13(iw_2, xenc6);
not g14(iw_3, n20);
not g15(iw_4, N2);
not g16(iw_5, N7);
not g17(iw_6, n15);
not g18(iw_7, n16);
not g19(iw_8, n19);
not g20(iw_9, xenc4);
and g21(xenc0, iw_8, keyinput0);
or g22(xenc1, n12, keyinput1);
or g23(xenc2, iw_7, keyinput2);
and g24(N22, xenc3, keyinput3);
or g25(xenc4, n18, keyinput4);
or g26(xenc5, iw_0, keyinput5);
or g27(xenc6, n17, keyinput6);
and g28(xenc7, n13, keyinput7);
endmodule
48 changes: 48 additions & 0 deletions benchmarks/c17/c17_lut_8bit.v
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// Verilog File
module c17_lut_8bit.bench (N1,N2,N3,N6,N7,keyinput0_1,keyinput0_0,keyinput1_0,keyinput2_0,
keyinput3_0,keyinput1_1,keyinput2_1,keyinput3_1,N22,N23);

input N1,N2,N3,N6,N7,keyinput0_1,keyinput0_0,keyinput1_0,keyinput2_0,
keyinput3_0,keyinput1_1,keyinput2_1,keyinput3_1;


output N22, N23;

wire n14, iw_0, iw_1, iw_2, iw_3, n12, iw_4, iw_5, n13,
iw_8, n15, n17, n18, n19, n20, iw_6, iw_9, iw_7, in0not_0,
in1not_0, T0_0, T1_0, T2_0, T3_0, in0not_1, in1not_1, T0_1, T1_1, T2_1,
T3_1;

not g0(N22, n14);
and g1(N23, iw_0, iw_1);
and g2(n12, iw_2, iw_3);
and g3(n13, iw_4, iw_5);
and g4(n15, iw_0, iw_8);
not g5(n17, N3);
not g6(n18, N1);
not g7(n19, N2);
not g8(n20, N6);
not g9(iw_0, n12);
not g10(iw_1, n13);
not g11(iw_2, n17);
not g12(iw_3, n20);
not g13(iw_4, N2);
not g14(iw_5, N7);
not g15(iw_6, n15);
not g16(iw_8, n19);
not g17(iw_9, n18);
not g18(in0not_0, iw_7);
not g19(in1not_0, iw_6);
and g20(T0_0, keyinput0_0, in0not_0, in1not_0);
and g21(T1_0, keyinput1_0, iw_7, in1not_0);
and g22(T2_0, keyinput2_0, in0not_0, iw_6);
and g23(T3_0, keyinput3_0, iw_7, iw_6);
or g24(n14, T0_0, T1_0, T2_0, T3_0);
not g25(in0not_1, iw_9);
not g26(in1not_1, iw_2);
and g27(T0_1, keyinput0_1, in0not_1, in1not_1);
and g28(T1_1, keyinput1_1, iw_9, in1not_1);
and g29(T2_1, keyinput2_1, in0not_1, iw_2);
and g30(T3_1, keyinput3_1, iw_9, iw_2);
or g31(iw_7, T0_1, T1_1, T2_1, T3_1);
endmodule
44 changes: 44 additions & 0 deletions benchmarks/c17/c17_xor_8bit.v
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// Verilog File
module c17_xor_8bit.bench (N1,N2,N3,N6,N7,keyinput0,keyinput1,keyinput2,keyinput3,
keyinput4,keyinput5,keyinput6,keyinput7,N22,N23);

input N1,N2,N3,N6,N7,keyinput0,keyinput1,keyinput2,keyinput3,
keyinput4,keyinput5,keyinput6,keyinput7;


output N22, N23;

wire n14, xenc4, iw_0, xenc6, iw_2, iw_3, n12, xenc5, iw_5,
n13, xenc2, xenc7, xenc3, n15, iw_9, n16, n17, n18, n19,
n20, iw_1, xenc0, iw_4, xenc1, iw_6, iw_7, iw_8;

not g0(xenc4, n14);
and g1(N23, iw_0, xenc6);
and g2(n12, iw_2, iw_3);
and g3(n13, xenc5, iw_5);
and g4(n14, xenc2, xenc7);
and g5(n15, iw_0, xenc3);
and g6(n16, iw_2, iw_9);
not g7(n17, N3);
not g8(n18, N1);
not g9(n19, N2);
not g10(n20, N6);
not g11(iw_0, n12);
not g12(iw_1, n13);
not g13(iw_2, xenc0);
not g14(iw_3, n20);
not g15(iw_4, N2);
not g16(iw_5, N7);
not g17(iw_6, xenc1);
not g18(iw_7, n16);
not g19(iw_8, n19);
not g20(iw_9, n18);
xor g21(xenc0, n17, keyinput0);
xor g22(xenc1, n15, keyinput1);
xor g23(xenc2, iw_6, keyinput2);
xnor g24(xenc3, iw_8, keyinput3);
xnor g25(N22, xenc4, keyinput4);
xnor g26(xenc5, iw_4, keyinput5);
xor g27(xenc6, iw_1, keyinput6);
xnor g28(xenc7, iw_7, keyinput7);
endmodule
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