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1. fpgacapZero fpgacapZero Public

   Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI

   Python 54 3

2. mjpegZero mjpegZero Public

   Open source synthesizable MJPEG encoder written in behavioral Verilog 2001 with AXI interfaces, up to 1080p30 on low end AMD/Xilinx 7-Series FPGAs. Two operating modes: Full encodes with runtime qu…

   Verilog 6 1

3. emacZero emacZero Public

   Open-source Verilog Ethernet MAC with AXI4-Stream, AXI4-Lite CSR, MDIO, MII to RGMII support, jumbo frames, and stats.

   Verilog 1

4. hdldiagZero hdldiagZero Public

   An agent skill that turns an HDL / RTL / SoC architecture description into a clean SVG block diagram

   Python 8

5. fpgaZeroMCP fpgaZeroMCP Public

   An open-source Model Context Protocol server that gives AI assistants a complete FPGA toolchain — lint, simulate, synthesize, place-and-route, and a live IP core registry backed by GitHub.

   Python 3 2

6. fresca fresca Public

   Versatile multi-sensor temperature controller

   C++ 11 2