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6 changes: 0 additions & 6 deletions arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -1529,9 +1529,3 @@
&cluster_pd2 {
domain-idle-states = <>;
};

&pon_resin {
linux,code = <KEY_VOLUMEDOWN>;

status = "okay";
};
8 changes: 8 additions & 0 deletions debian.qcom-x1e/changelog
Original file line number Diff line number Diff line change
@@ -1,3 +1,11 @@
linux-qcom-x1e (7.2.2-jg-0sp11v21) resolute; urgency=medium

* Fix the Denali volume-down replay by leaving pon_resin disabled.
* Preserve the GPI DMA_PRIVATE capability and GENI SPI tracepoints in the
SP11 QSPI port.

-- Leon Silcott <leon@boasi.io> Mon, 31 Aug 2026 14:15:14 +0100

linux-qcom-x1e (7.2.2-jg-0sp11v20) resolute; urgency=medium

* rebased the PR onto jg/ubunt-qcom-x1e-7.2.y
Expand Down
1 change: 1 addition & 0 deletions drivers/dma/qcom/gpi.c
Original file line number Diff line number Diff line change
Expand Up @@ -2747,6 +2747,7 @@ static int gpi_probe(struct platform_device *pdev)
/* clear and Set capabilities */
dma_cap_zero(gpi_dev->dma_device.cap_mask);
dma_cap_set(DMA_SLAVE, gpi_dev->dma_device.cap_mask);
dma_cap_set(DMA_PRIVATE, gpi_dev->dma_device.cap_mask);

/* configure dmaengine apis */
gpi_dev->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
Expand Down
13 changes: 13 additions & 0 deletions drivers/spi/spi-geni-qcom.c
Original file line number Diff line number Diff line change
@@ -1,6 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.

#define CREATE_TRACE_POINTS
#include <trace/events/qcom_geni_spi.h>

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
Expand Down Expand Up @@ -463,6 +466,9 @@ static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas,
writel(clk_sel, se->base + SE_GENI_CLK_SEL);
writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);

trace_geni_spi_clk_cfg(mas->dev, clk_hz, mas->cur_sclk_hz, idx, div,
mas->cur_bits_per_word);

/* Set BW quota for CPU as driver supports FIFO mode only. */
se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
ret = geni_icc_set_bw(se);
Expand Down Expand Up @@ -497,6 +503,9 @@ static int setup_fifo_params(struct spi_device *spi_slv,
if ((mode_changed & SPI_CS_HIGH) || (cs_changed && (spi_slv->mode & SPI_CS_HIGH)))
writel((spi_slv->mode & SPI_CS_HIGH) ? BIT(chipselect) : 0, se->base + SE_SPI_DEMUX_OUTPUT_INV);

trace_geni_spi_setup_params(mas->dev, chipselect, spi_slv->mode,
mode_changed, cs_changed);

return 0;
}

Expand Down Expand Up @@ -1412,6 +1421,8 @@ static int setup_se_xfer(struct spi_transfer *xfer,
spin_lock_irq(&mas->lock);
geni_se_setup_m_cmd(se, m_cmd, m_params);

trace_geni_spi_transfer(mas->dev, len, m_cmd);

if (mas->cur_xfer_mode == GENI_SE_DMA) {
if (m_cmd & SPI_RX_ONLY)
geni_se_rx_init_dma(se, sg_dma_address(xfer->rx_sg.sgl),
Expand Down Expand Up @@ -1466,6 +1477,8 @@ static irqreturn_t geni_spi_isr(int irq, void *data)
if (!m_irq && !dma_tx_status && !dma_rx_status)
return IRQ_NONE;

trace_geni_spi_irq(mas->dev, m_irq, dma_tx_status, dma_rx_status);

if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |
M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN |
M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN))
Expand Down