EE student at Purdue passionate about Digital Design, DSP, RF, and embedded systems.
Highlights
- Pro
Pinned Loading
-
-
fpga-audio-effects
fpga-audio-effects PublicMy specific contributions and work on the Harmonicore FPGA project.
SystemVerilog
-
HarmoniCore2.0-Jeans-Fork
HarmoniCore2.0-Jeans-Fork PublicForked from embedded-purdue/HarmoniCore2.0
Fork of Embedded Systems @ Purdue's Harmonicore Project and my contributions to it.
VHDL
-
socet-1-shot-clock-fork
socet-1-shot-clock-fork PublicForked from wadhwat/socet-1-shot-clock
SystemVerilog
-
-
WiFi-Coverage-Simulation-
WiFi-Coverage-Simulation- PublicSimulates a WiFi router's signal through an area with obstacles of different materials.
Python
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.