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tests: Update enc= values to preserve useless 0x67 address-size prefix#804

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mattst88:encoder-test-updates
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tests: Update enc= values to preserve useless 0x67 address-size prefix#804
mattst88 wants to merge 5 commits into
icedland:masterfrom
mattst88:encoder-test-updates

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@mattst88 mattst88 commented Jun 12, 2026

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Summary

  • Update 25 enc= entries in DecoderTest{16,32,64}.txt to include the leading 67 byte
  • These entries have a 0x67 prefix in the original bytes; with has_address_size_prefix now preserved through encode, the re-encoded bytes include 67 and the test expectations must match

Depends on: #802, #803

Test plan

  • cargo test -p iced-x86 -- encode_16 encode_32 encode_64 passes

mattst88 added 5 commits June 12, 2026 09:34
Track whether the original encoding contained a 0x67 address-size prefix
that had no semantic effect (i.e. the instruction has no memory
operand). Backed by a free bit (bit 20) in InstrFlags1::flags1,
following the same pattern as has_lock_prefix.
…0x67

OpCodeHandler_Prefix67 flips the address size and delegates to the real
opcode handler. If the decoded instruction has no memory operand of any
kind (OpKind >= MemorySegSI), the 0x67 byte had no semantic effect and
was previously silently discarded. Record it via has_address_size_prefix
so the encoder and formatters can reproduce the original bytes.
Extend write_prefixes() to emit the address-size prefix byte when
instruction.has_address_size_prefix() is true, in addition to the
existing EncoderFlags::P67 path that handles memory operands.
When has_address_size_prefix() is true and show_useless_prefixes is
enabled, emit the NASM address-size keyword (a16 in 32-bit mode, a32
otherwise) so NASM can reproduce the original 0x67-prefixed bytes.
For 25 decoder test entries that have a 0x67 prefix on a non-memory
instruction, the enc= field previously specified the canonical form with
0x67 stripped. Now that the encoder round-trips has_address_size_prefix,
update all enc= values to include the leading 67 byte.

Affected entries:
- 22 x "66 67 4E <rm8-r8 ops>" in DecoderTest64.txt
- "67 8F E9 78 12 C3" (XOP Llwpcb_r32) in all three bitness files
- "67 8F E9 F8 12 C3" (XOP Llwpcb_r64) in DecoderTest64.txt
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