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[Explicit State Access] Support multiple state reads in ir_parser.cc and ir_minimizer_main.cc. #4715

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[Explicit State Access] Support multiple state reads in ir_parser.cc and ir_minimizer_main.cc. #4715

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1 change: 1 addition & 0 deletions xls/codegen_v_1_5/state_to_register_io_lowering_pass.cc
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Expand Up @@ -73,6 +73,7 @@ absl::StatusOr<bool> ReplaceNode(Block* block, Node* old_node, Node* new_node,

if (old_node->Is<StateRead>()) {
XLS_RETURN_IF_ERROR(block->RemoveNodeFromStage(old_node).status());
XLS_RETURN_IF_ERROR(old_node->function_base()->RemoveNode(old_node));
return false;
}
if (old_node->IsDead()) {
Expand Down
22 changes: 11 additions & 11 deletions ...degen_v_1_5/testdata/scheduled_block_conversion_pass_test_SimpleProcWithGlobalChannels.ir
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Expand Up @@ -9,10 +9,10 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
source proc __test__P_0_next__src(__state: bits[32], init={0}) {
}
literal.3: bits[1] = literal(value=1, id=3)
stage_inputs_valid_0: bits[1] = literal(value=1, id=19)
stage_outputs_ready_0: bits[1] = literal(value=1, id=20)
stage_inputs_valid_0: bits[1] = literal(value=1, id=20)
stage_outputs_ready_0: bits[1] = literal(value=1, id=21)
controlled_stage(stage_inputs_valid_0, stage_outputs_ready_0) {
active_inputs_valid active_inputs_valid_0: bits[1] = literal(value=1, id=21)
active_inputs_valid active_inputs_valid_0: bits[1] = literal(value=1, id=22)
after_all.4: token = after_all(id=4)
receive.5: (token, bits[32]) = receive(after_all.4, predicate=literal.3, channel=test__a, id=5)
tok: token = tuple_index(receive.5, index=0, id=7)
Expand All @@ -21,17 +21,17 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
tok__1: token = tuple_index(receive.9, index=0, id=11)
b_value: bits[32] = tuple_index(receive.9, index=1, id=12)
umul.13: bits[32] = umul(a_value, b_value, id=13)
ret stage_outputs_valid_0: bits[1] = and(stage_inputs_valid_0, active_inputs_valid_0, id=22)
ret stage_outputs_valid_0: bits[1] = and(stage_inputs_valid_0, active_inputs_valid_0, id=23)
}
stage_inputs_valid_1: bits[1] = literal(value=1, id=23)
stage_outputs_ready_1: bits[1] = literal(value=1, id=24)
stage_inputs_valid_1: bits[1] = literal(value=1, id=24)
stage_outputs_ready_1: bits[1] = literal(value=1, id=25)
controlled_stage(stage_inputs_valid_1, stage_outputs_ready_1) {
active_inputs_valid active_inputs_valid_1: bits[1] = literal(value=1, id=25)
__state: bits[32] = state_read(state_element=__state, id=2)
result_value: bits[32] = add(umul.13, __state, id=14)
active_inputs_valid active_inputs_valid_1: bits[1] = literal(value=1, id=26)
__state__1: bits[32] = state_read(state_element=__state, id=2)
result_value: bits[32] = add(umul.13, __state__1, id=14)
send.15: token = send(tok__1, result_value, predicate=literal.3, channel=test__result, id=15)
next_value.16: () = next_value(state_element=__state, value=result_value, id=16)
ret stage_outputs_valid_1: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=26)
ret stage_outputs_valid_1: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=27)
}
rst: bits[1] = input_port(name=rst, id=18)
rst: bits[1] = input_port(name=rst, id=19)
}
22 changes: 11 additions & 11 deletions ...n_v_1_5/testdata/scheduled_block_conversion_pass_test_SimpleProcWithProcScopedChannels.ir
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Expand Up @@ -8,10 +8,10 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
chan_interface result(direction=send, kind=streaming, strictness=proven_mutually_exclusive, flow_control=ready_valid, flop_kind=none)
}
literal.3: bits[1] = literal(value=1, id=3)
stage_inputs_valid_0: bits[1] = literal(value=1, id=20)
stage_outputs_ready_0: bits[1] = literal(value=1, id=21)
stage_inputs_valid_0: bits[1] = literal(value=1, id=21)
stage_outputs_ready_0: bits[1] = literal(value=1, id=22)
controlled_stage(stage_inputs_valid_0, stage_outputs_ready_0) {
active_inputs_valid active_inputs_valid_0: bits[1] = literal(value=1, id=22)
active_inputs_valid active_inputs_valid_0: bits[1] = literal(value=1, id=23)
after_all.5: token = after_all(id=5)
receive.6: (token, bits[32]) = receive(after_all.5, predicate=literal.3, channel=a, id=6)
tok: token = tuple_index(receive.6, index=0, id=8)
Expand All @@ -20,17 +20,17 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
tok__1: token = tuple_index(receive.10, index=0, id=12)
b_value: bits[32] = tuple_index(receive.10, index=1, id=13)
umul.14: bits[32] = umul(a_value, b_value, id=14)
ret stage_outputs_valid_0: bits[1] = and(stage_inputs_valid_0, active_inputs_valid_0, id=23)
ret stage_outputs_valid_0: bits[1] = and(stage_inputs_valid_0, active_inputs_valid_0, id=24)
}
stage_inputs_valid_1: bits[1] = literal(value=1, id=24)
stage_outputs_ready_1: bits[1] = literal(value=1, id=25)
stage_inputs_valid_1: bits[1] = literal(value=1, id=25)
stage_outputs_ready_1: bits[1] = literal(value=1, id=26)
controlled_stage(stage_inputs_valid_1, stage_outputs_ready_1) {
active_inputs_valid active_inputs_valid_1: bits[1] = literal(value=1, id=26)
__state: bits[32] = state_read(state_element=__state, id=2)
result_value: bits[32] = add(umul.14, __state, id=15)
active_inputs_valid active_inputs_valid_1: bits[1] = literal(value=1, id=27)
__state__1: bits[32] = state_read(state_element=__state, id=2)
result_value: bits[32] = add(umul.14, __state__1, id=15)
send.16: token = send(tok__1, result_value, predicate=literal.3, channel=result, id=16)
next_value.17: () = next_value(state_element=__state, value=result_value, id=17)
ret stage_outputs_valid_1: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=27)
ret stage_outputs_valid_1: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=28)
}
rst: bits[1] = input_port(name=rst, id=19)
rst: bits[1] = input_port(name=rst, id=20)
}
20 changes: 10 additions & 10 deletions xls/codegen_v_1_5/testdata/scheduled_block_conversion_pass_test_SimpleProcWithoutReset.ir
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Expand Up @@ -7,10 +7,10 @@ top scheduled_block __test__P_0_next(clk: clock) {
chan_interface result(direction=send, kind=streaming, strictness=proven_mutually_exclusive, flow_control=ready_valid, flop_kind=none)
}
literal.3: bits[1] = literal(value=1, id=3)
stage_inputs_valid_0: bits[1] = literal(value=1, id=19)
stage_outputs_ready_0: bits[1] = literal(value=1, id=20)
stage_inputs_valid_0: bits[1] = literal(value=1, id=20)
stage_outputs_ready_0: bits[1] = literal(value=1, id=21)
controlled_stage(stage_inputs_valid_0, stage_outputs_ready_0) {
active_inputs_valid active_inputs_valid_0: bits[1] = literal(value=1, id=21)
active_inputs_valid active_inputs_valid_0: bits[1] = literal(value=1, id=22)
after_all.5: token = after_all(id=5)
receive.6: (token, bits[32]) = receive(after_all.5, predicate=literal.3, channel=a, id=6)
tok: token = tuple_index(receive.6, index=0, id=8)
Expand All @@ -19,16 +19,16 @@ top scheduled_block __test__P_0_next(clk: clock) {
tok__1: token = tuple_index(receive.10, index=0, id=12)
b_value: bits[32] = tuple_index(receive.10, index=1, id=13)
umul.14: bits[32] = umul(a_value, b_value, id=14)
ret stage_outputs_valid_0: bits[1] = and(stage_inputs_valid_0, active_inputs_valid_0, id=22)
ret stage_outputs_valid_0: bits[1] = and(stage_inputs_valid_0, active_inputs_valid_0, id=23)
}
stage_inputs_valid_1: bits[1] = literal(value=1, id=23)
stage_outputs_ready_1: bits[1] = literal(value=1, id=24)
stage_inputs_valid_1: bits[1] = literal(value=1, id=24)
stage_outputs_ready_1: bits[1] = literal(value=1, id=25)
controlled_stage(stage_inputs_valid_1, stage_outputs_ready_1) {
active_inputs_valid active_inputs_valid_1: bits[1] = literal(value=1, id=25)
__state: bits[32] = state_read(state_element=__state, id=2)
result_value: bits[32] = add(umul.14, __state, id=15)
active_inputs_valid active_inputs_valid_1: bits[1] = literal(value=1, id=26)
__state__1: bits[32] = state_read(state_element=__state, id=2)
result_value: bits[32] = add(umul.14, __state__1, id=15)
send.16: token = send(tok__1, result_value, predicate=literal.3, channel=result, id=16)
next_value.17: () = next_value(state_element=__state, value=result_value, id=17)
ret stage_outputs_valid_1: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=26)
ret stage_outputs_valid_1: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=27)
}
}
4 changes: 2 additions & 2 deletions xls/codegen_v_1_5/testdata/scheduling_pass_test_MultiProcWithOneProcScheduled.ir
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Expand Up @@ -17,8 +17,8 @@ top scheduled_proc __test__P_0_next(__state: bits[32], init={0}) {
umul.13: bits[32] = umul(a_value, b_value, id=13)
}
stage {
__state: bits[32] = state_read(state_element=__state, id=2)
result_value: bits[32] = add(umul.13, __state, id=14)
__state__1: bits[32] = state_read(state_element=__state, id=2)
result_value: bits[32] = add(umul.13, __state__1, id=14)
send.15: token = send(tok__1, result_value, predicate=literal.3, channel=test__result, id=15)
next_value.16: () = next_value(state_element=__state, value=result_value, id=16)
}
Expand Down
4 changes: 2 additions & 2 deletions xls/codegen_v_1_5/testdata/scheduling_pass_test_SimpleProcWithGlobalChannels.ir
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Expand Up @@ -17,8 +17,8 @@ top scheduled_proc __test__P_0_next(__state: bits[32], init={0}) {
umul.13: bits[32] = umul(a_value, b_value, id=13)
}
stage {
__state: bits[32] = state_read(state_element=__state, id=2)
result_value: bits[32] = add(umul.13, __state, id=14)
__state__1: bits[32] = state_read(state_element=__state, id=2)
result_value: bits[32] = add(umul.13, __state__1, id=14)
send.15: token = send(tok__1, result_value, predicate=literal.3, channel=test__result, id=15)
next_value.16: () = next_value(state_element=__state, value=result_value, id=16)
}
Expand Down
4 changes: 2 additions & 2 deletions xls/codegen_v_1_5/testdata/scheduling_pass_test_SimpleProcWithProcScopedChannels.ir
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Expand Up @@ -16,8 +16,8 @@ top scheduled_proc __test__P_0_next<a: bits[32] in, b: bits[32] in, result: bits
umul.14: bits[32] = umul(a_value, b_value, id=14)
}
stage {
__state: bits[32] = state_read(state_element=__state, id=2)
result_value: bits[32] = add(umul.14, __state, id=15)
__state__1: bits[32] = state_read(state_element=__state, id=2)
result_value: bits[32] = add(umul.14, __state__1, id=15)
send.16: token = send(tok__1, result_value, predicate=literal.3, channel=result, id=16)
next_value.17: () = next_value(state_element=__state, value=result_value, id=17)
}
Expand Down
18 changes: 9 additions & 9 deletions xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithFullBitForToken.ir
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Expand Up @@ -27,23 +27,23 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
stage_inputs_valid_1: bits[1] = literal(value=1, id=24)
stage_outputs_ready_1: bits[1] = literal(value=1, id=25)
controlled_stage(stage_inputs_valid_1, stage_outputs_ready_1) {
active_inputs_valid ____state_full: bits[1] = register_read(register=____state_full, id=44)
active_inputs_valid ____state_full: bits[1] = register_read(register=____state_full, id=45)
send.16: token = send(tok__1, umul.14, predicate=literal.3, channel=result, id=16)
ret stage_outputs_valid_1: bits[1] = and(stage_inputs_valid_1, ____state_full, id=27)
}
stage_inputs_valid_2: bits[1] = literal(value=1, id=28)
stage_outputs_ready_2: bits[1] = literal(value=1, id=29)
controlled_stage(stage_inputs_valid_2, stage_outputs_ready_2) {
active_inputs_valid active_inputs_valid_2: bits[1] = literal(value=1, id=30)
identity.46: token = identity(tok, id=46)
identity.47: token = identity(tok, id=47)
ret stage_outputs_valid_2: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=32)
}
rst: bits[1] = input_port(name=rst, id=19)
literal.43: token = literal(value=token, id=43)
and.45: bits[1] = and(stage_outputs_valid_2, stage_outputs_ready_2, id=45)
and.47: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=47)
tuple.48: () = tuple(id=48)
and.49: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=49)
or.50: bits[1] = or(and.49, and.45, id=50)
register_write.51: () = register_write(and.45, register=____state_full, load_enable=or.50, reset=rst, id=51)
literal.44: token = literal(value=token, id=44)
and.46: bits[1] = and(stage_outputs_valid_2, stage_outputs_ready_2, id=46)
and.48: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=48)
tuple.49: () = tuple(id=49)
and.50: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=50)
or.51: bits[1] = or(and.50, and.46, id=51)
register_write.52: () = register_write(and.46, register=____state_full, load_enable=or.51, reset=rst, id=52)
}
10 changes: 5 additions & 5 deletions xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithNonZeroInitValue.ir
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Expand Up @@ -28,14 +28,14 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
stage_outputs_ready_1: bits[1] = literal(value=1, id=25)
controlled_stage(stage_inputs_valid_1, stage_outputs_ready_1) {
active_inputs_valid active_inputs_valid_1: bits[1] = literal(value=1, id=26)
____state__1: bits[32] = register_read(register=____state, id=40)
____state__1: bits[32] = register_read(register=____state, id=41)
result_value: bits[32] = add(umul.14, ____state__1, id=15)
send.16: token = send(tok__1, result_value, predicate=literal.3, channel=result, id=16)
ret stage_outputs_valid_1: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=27)
}
rst: bits[1] = input_port(name=rst, id=19)
and.41: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=41)
and.42: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=42)
register_write.43: () = register_write(result_value, register=____state, load_enable=and.41, reset=rst, id=43)
tuple.44: () = tuple(id=44)
and.42: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=42)
and.43: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=43)
register_write.44: () = register_write(result_value, register=____state, load_enable=and.42, reset=rst, id=44)
tuple.45: () = tuple(id=45)
}
20 changes: 10 additions & 10 deletions xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithFullBit.ir
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Expand Up @@ -29,8 +29,8 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
stage_inputs_valid_1: bits[1] = literal(value=1, id=24)
stage_outputs_ready_1: bits[1] = literal(value=1, id=25)
controlled_stage(stage_inputs_valid_1, stage_outputs_ready_1) {
active_inputs_valid ____state_full: bits[1] = register_read(register=____state_full, id=45)
____state__1: bits[32] = register_read(register=____state, id=44)
active_inputs_valid ____state_full: bits[1] = register_read(register=____state_full, id=46)
____state__1: bits[32] = register_read(register=____state, id=45)
result_value: bits[32] = add(umul.14, ____state__1, id=15)
send.16: token = send(tok__1, result_value, predicate=literal.3, channel=result, id=16)
ret stage_outputs_valid_1: bits[1] = and(stage_inputs_valid_1, ____state_full, id=27)
Expand All @@ -39,15 +39,15 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
stage_outputs_ready_2: bits[1] = literal(value=1, id=29)
controlled_stage(stage_inputs_valid_2, stage_outputs_ready_2) {
active_inputs_valid active_inputs_valid_2: bits[1] = literal(value=1, id=30)
identity.47: bits[32] = identity(result_value, id=47)
identity.48: bits[32] = identity(result_value, id=48)
ret stage_outputs_valid_2: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=32)
}
rst: bits[1] = input_port(name=rst, id=19)
and.46: bits[1] = and(stage_outputs_valid_2, stage_outputs_ready_2, id=46)
and.48: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=48)
register_write.49: () = register_write(identity.47, register=____state, load_enable=and.46, reset=rst, id=49)
tuple.50: () = tuple(id=50)
and.51: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=51)
or.52: bits[1] = or(and.51, and.46, id=52)
register_write.53: () = register_write(and.46, register=____state_full, load_enable=or.52, reset=rst, id=53)
and.47: bits[1] = and(stage_outputs_valid_2, stage_outputs_ready_2, id=47)
and.49: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=49)
register_write.50: () = register_write(identity.48, register=____state, load_enable=and.47, reset=rst, id=50)
tuple.51: () = tuple(id=51)
and.52: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=52)
or.53: bits[1] = or(and.52, and.47, id=53)
register_write.54: () = register_write(and.47, register=____state_full, load_enable=or.53, reset=rst, id=54)
}
26 changes: 13 additions & 13 deletions ...n_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithFullBitAndPredicates.ir
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Expand Up @@ -30,10 +30,10 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
stage_inputs_valid_1: bits[1] = literal(value=1, id=40)
stage_outputs_ready_1: bits[1] = literal(value=1, id=41)
controlled_stage(stage_inputs_valid_1, stage_outputs_ready_1) {
____state_full: bits[1] = register_read(register=____state_full, id=74)
not.75: bits[1] = not(ugt.16, id=75)
active_inputs_valid active_inputs_valid_1: bits[1] = or(____state_full, not.75, id=76)
____state__1: bits[32] = register_read(register=____state, id=73)
____state_full: bits[1] = register_read(register=____state_full, id=75)
not.76: bits[1] = not(ugt.16, id=76)
active_inputs_valid active_inputs_valid_1: bits[1] = or(____state_full, not.76, id=77)
____state__1: bits[32] = register_read(register=____state, id=74)
__token: token = literal(value=token, id=1)
tuple.4: () = tuple(id=4)
tuple_index.7: token = tuple_index(receive.6, index=0, id=7)
Expand All @@ -53,16 +53,16 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
stage_outputs_ready_2: bits[1] = literal(value=1, id=29)
controlled_stage(stage_inputs_valid_2, stage_outputs_ready_2) {
active_inputs_valid active_inputs_valid_2: bits[1] = literal(value=1, id=30)
identity.78: bits[32] = identity(sel.24, id=78)
identity.79: bits[1] = identity(ugt.22, id=79)
identity.79: bits[32] = identity(sel.24, id=79)
identity.80: bits[1] = identity(ugt.22, id=80)
ret stage_outputs_valid_2: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=43)
}
rst: bits[1] = input_port(name=rst, id=35)
and.77: bits[1] = and(stage_outputs_valid_2, stage_outputs_ready_2, ugt.22, id=77)
and.80: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, identity.79, id=80)
register_write.81: () = register_write(identity.78, register=____state, load_enable=and.77, reset=rst, id=81)
tuple.82: () = tuple(id=82)
and.83: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, ugt.16, id=83)
or.84: bits[1] = or(and.83, and.77, id=84)
register_write.85: () = register_write(and.77, register=____state_full, load_enable=or.84, reset=rst, id=85)
and.78: bits[1] = and(stage_outputs_valid_2, stage_outputs_ready_2, ugt.22, id=78)
and.81: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, identity.80, id=81)
register_write.82: () = register_write(identity.79, register=____state, load_enable=and.78, reset=rst, id=82)
tuple.83: () = tuple(id=83)
and.84: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, ugt.16, id=84)
or.85: bits[1] = or(and.84, and.78, id=85)
register_write.86: () = register_write(and.78, register=____state_full, load_enable=or.85, reset=rst, id=86)
}
10 changes: 5 additions & 5 deletions ...codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithGlobalChannels.ir
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Expand Up @@ -29,14 +29,14 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
stage_outputs_ready_1: bits[1] = literal(value=1, id=24)
controlled_stage(stage_inputs_valid_1, stage_outputs_ready_1) {
active_inputs_valid active_inputs_valid_1: bits[1] = literal(value=1, id=25)
____state__1: bits[32] = register_read(register=____state, id=39)
____state__1: bits[32] = register_read(register=____state, id=40)
result_value: bits[32] = add(umul.13, ____state__1, id=14)
send.15: token = send(tok__1, result_value, predicate=literal.3, channel=test__result, id=15)
ret stage_outputs_valid_1: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=26)
}
rst: bits[1] = input_port(name=rst, id=18)
and.40: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=40)
and.41: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=41)
register_write.42: () = register_write(result_value, register=____state, load_enable=and.40, reset=rst, id=42)
tuple.43: () = tuple(id=43)
and.41: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=41)
and.42: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=42)
register_write.43: () = register_write(result_value, register=____state, load_enable=and.41, reset=rst, id=43)
tuple.44: () = tuple(id=44)
}
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