Improve SVE2 optimizations of SimdFloat32ToBFloat16

[ermig1979]

Replace the SVE2 software rounding path of SimdFloat32ToBFloat16 with hardware BFloat16 conversion.

Changes

• Use svcvt_bf16_f32_x + svcvtnt_bf16_f32_x (BFCVT / BFCVTNT) in SimdSve2BFloat16.cpp instead of shift/add rounding.
• Deinterleave consecutive f32 vectors with svuzp1_f32 / svuzp2_f32 so the convert pair writes sequential bf16 values.
• Unroll the main loop by 4 destination vectors.
• Add the change to the Improving list of release 7.2.165 in docs/2026.html.

Test results

• AArch64 cross-compile of SimdSve2BFloat16.cpp emits bfcvt / bfcvtnt.
• QEMU user-mode SVE (VL 128/256/512): hardware svcvt/svcvtnt matches Base::Float32ToBFloat16 for 39 sizes per VL, including tails.
• Packing simulation of uzp1/uzp2 + even/odd convert matches Base for F=4/8/16 and aligned/tail sizes.
• Native x86 ./Test "-r=.." -fi=Float32ToBFloat16 -tt=1 -ts=1 -w=640 -h=480: ALL TESTS ARE FINISHED SUCCESSFULLY (Base / SSE4.1 / AVX2 / AVX-512BW / AMX).

Test log

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