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WinstonllllaiWinstonllllai
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feat: implement Lazy FPU Stacking and Vector Table
1 parent 6dee013 commit 85d0626

6 files changed

Lines changed: 839 additions & 682 deletions

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‎ports/risc-v32/gnu/src/tx_initialize_low_level.S‎

Lines changed: 45 additions & 59 deletions
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@@ -19,27 +19,12 @@
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/**************************************************************************/
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/**************************************************************************/
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/* Include necessary system files. */
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/* #include "tx_api.h"
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#include "tx_initialize.h"
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#include "tx_thread.h"
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#include "tx_timer.h" */
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.extern _tx_thread_system_stack_ptr
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.extern _tx_initialize_unused_memory
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.extern _tx_thread_context_save
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.extern _tx_thread_context_restore
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.extern _tx_timer_interrupt
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.section .bss
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.balign 4
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.globl __tx_free_memory_start
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.section .data
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.global __tx_free_memory_start
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__tx_free_memory_start:
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.space 4
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.section .text
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.balign 4
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
@@ -49,7 +34,6 @@ __tx_free_memory_start:
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/* AUTHOR */
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/* */
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/* Akif Ejaz, 10xEngineers */
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/* Wei-Chen Lai, National Cheng Kung University */
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/* */
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/* DESCRIPTION */
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/* */
@@ -75,64 +59,66 @@ __tx_free_memory_start:
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/* */
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/* _tx_initialize_kernel_enter ThreadX entry function */
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/* */
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/* RELEASE HISTORY */
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/* */
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/* DATE NAME DESCRIPTION */
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/* */
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/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */
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/* */
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/**************************************************************************/
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/* VOID _tx_initialize_low_level(VOID)
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{ */
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.globl _tx_initialize_low_level
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.global _tx_initialize_low_level
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.weak _tx_initialize_low_level
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_tx_initialize_low_level:
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la t0, _tx_thread_system_stack_ptr
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la t0, _tx_thread_system_stack_ptr // Pickup address of system stack ptr
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sw sp, 0(t0) // Save system stack pointer
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la t0, __tx_free_memory_start // Pickup first free address
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la t1, _tx_initialize_unused_memory
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la t1, _tx_initialize_unused_memory // Pickup address of unused memory
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sw t0, 0(t1) // Save unused memory address
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ret
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#if defined(__riscv_flen) && ((__riscv_flen == 32) || (__riscv_flen == 64))
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li t0, 0x00006000 // Set FS field of mstatus to 3 (Dirty)
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csrs mstatus, t0
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fscsr x0 // Clear the fcsr
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#endif
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la t0, _tx_trap_handler // Pickup trap handler address
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csrw mtvec, t0 // Store trap handler address
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ret
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/* Define the actual timer interrupt/exception handler. */
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.globl _tx_timer_interrupt_handler
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.globl __minterrupt_000007
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_tx_timer_interrupt_handler:
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__minterrupt_000007:
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.global _tx_trap_handler
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_tx_trap_handler:
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/* Before calling _tx_thread_context_save, we have to allocate an interrupt
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stack frame and save the current value of x1 (ra). */
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#if defined(__riscv_32e) || defined(__riscv_32rve)
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addi sp, sp, -260 // Allocate space for all registers - with floating point enabled
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//#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
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// addi sp, sp, -520 // Allocate space for all registers - with floating point enabled
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//#else
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// addi sp, sp, -256 // Allocate space for all registers - without floating point enabled
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//#endif
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// sd x1, 224(sp) // Store RA
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#if defined(__riscv_flen) && ((__riscv_flen == 32) || (__riscv_flen == 64))
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addi sp, sp, -65*REGBYTES // Allocate space for all registers - with floating point enabled
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#else
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addi sp, sp, -128 // Allocate space for all registers - without floating point enabled
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addi sp, sp, -32*REGBYTES // Allocate space for all registers - without floating point enabled
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#endif
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sw x1, 0x70(sp) // Store RA
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call _tx_thread_context_save // Call ThreadX context save
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STORE x1, 28*REGBYTES(sp)
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call _tx_thread_context_save // Call ThreadX context save
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csrr t0, mcause // Pickup mcause
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li t1, 0x80000007
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beq t0, t1, _tx_timer_handler_entry // If mcause is Timer Interrupt, call timer interrupt handler
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j _tx_trap_exit
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/* Call the ThreadX timer routine. */
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call _tx_timer_interrupt // Call timer interrupt handler
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_tx_timer_handler_entry:
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call _tx_timer_interrupt // Call timer interrupt handler
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/* Timer interrupt processing is done, jump to ThreadX context restore. */
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tail _tx_thread_context_restore // Jump to ThreadX context restore function. Note: this does not return!
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/* Timer Interrupt Handler Note:
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Platform-specific implementations must provide their own timer ISR.
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The timer interrupt handler should follow this execution flow:
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1. Disable interrupts (if not done by hardware exception entry)
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2. Allocate interrupt stack frame (65*4 bytes with FP, 32*4 bytes without)
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3. Save RA (x1) on the stack at offset 28*4
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4. Call _tx_thread_context_save to save thread context
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5. Call _tx_timer_interrupt to process the timer tick
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6. Call _tx_thread_context_restore to resume execution (does not return)
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Example (for CLINT timer):
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_tx_timer_interrupt_handler:
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addi sp, sp, -32*4
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sw ra, 28*4(sp)
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call _tx_thread_context_save
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call _tx_timer_interrupt
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j _tx_thread_context_restore
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The port assumes Machine mode (M-mode) execution.
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For Supervisor mode (S-mode), use sstatus and SIE/SPIE instead of mstatus.
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See the RISC-V Privileged Specification for more details. */
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_tx_trap_exit:
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j _tx_thread_context_restore // Jump to ThreadX context restore function. Note: this does not return!

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