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docs: resolve merge conflicts in RISC-V 32-bit GNU port files
1 parent 3726d79 commit 6dee013

9 files changed

Lines changed: 822 additions & 906 deletions

‎ports/risc-v32/gnu/inc/tx_port.h‎

Lines changed: 26 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@
3030
/* AUTHOR */
3131
/* */
3232
/* Akif Ejaz, 10xEngineers */
33+
/* Wei-Chen Lai, National Cheng Kung University */
3334
/* */
3435
/* DESCRIPTION */
3536
/* */
@@ -229,36 +230,37 @@ typedef unsigned short USHORT;
229230
is used to define a local function save area for the disable and restore
230231
macros. */
231232

232-
/* Expose helper used to perform an atomic read/modify/write of mstatus.
233-
The helper composes and returns the posture per ThreadX contract. */
234-
#ifndef __ASSEMBLER__
235-
UINT _tx_thread_interrupt_control(UINT new_posture);
236-
#endif
237-
238233
#ifdef TX_DISABLE_INLINE
239234

240-
#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save;
241-
242-
#define TX_DISABLE __asm__ volatile("csrrci %0, mstatus, 8" : "=r" (interrupt_save) :: "memory");
243-
#define TX_RESTORE { \
244-
unsigned long _temp_mstatus; \
245-
__asm__ volatile( \
246-
"csrc mstatus, 8\n" \
247-
"andi %0, %1, 8\n" \
248-
"csrs mstatus, %0" \
249-
: "=&r" (_temp_mstatus) \
250-
: "r" (interrupt_save) \
251-
: "memory"); \
252-
}
253-
254-
#else
235+
unsigned int _tx_thread_interrupt_control(unsigned int new_posture);
255236

256-
#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save;
237+
#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save;
257238

258239
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE);
259240
#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save);
260241

261-
#endif /* TX_DISABLE_INLINE */
242+
#else
243+
244+
#define TX_INTERRUPT_SAVE_AREA ULONG interrupt_save;
245+
246+
#define TX_DISABLE \
247+
__asm__ volatile ( \
248+
"csrr %0, mstatus\n\t" \
249+
"csrci mstatus, 8" \
250+
: "=r" (interrupt_save) \
251+
: \
252+
: "memory" \
253+
);
254+
255+
#define TX_RESTORE \
256+
__asm__ volatile ( \
257+
"csrw mstatus, %0\n\t" \
258+
: \
259+
: "r" (interrupt_save) \
260+
: "memory" \
261+
);
262+
263+
#endif
262264

263265

264266
/* Define the interrupt lockout macros for each ThreadX object. */
@@ -282,4 +284,4 @@ extern CHAR _tx_version_id[];
282284
#endif /* TX_THREAD_INIT */
283285
#endif /* __ASSEMBLER__ */
284286

285-
#endif /* TX_PORT_H */
287+
#endif /* TX_PORT_H */

‎ports/risc-v32/gnu/src/tx_initialize_low_level.S‎

Lines changed: 46 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -19,12 +19,27 @@
1919
/**************************************************************************/
2020
/**************************************************************************/
2121

22-
.section .data
23-
.global __tx_free_memory_start
22+
/* Include necessary system files. */
23+
24+
/* #include "tx_api.h"
25+
#include "tx_initialize.h"
26+
#include "tx_thread.h"
27+
#include "tx_timer.h" */
28+
29+
.extern _tx_thread_system_stack_ptr
30+
.extern _tx_initialize_unused_memory
31+
.extern _tx_thread_context_save
32+
.extern _tx_thread_context_restore
33+
.extern _tx_timer_interrupt
34+
35+
.section .bss
36+
.balign 4
37+
.globl __tx_free_memory_start
2438
__tx_free_memory_start:
25-
39+
.space 4
2640

2741
.section .text
42+
.balign 4
2843
/**************************************************************************/
2944
/* */
3045
/* FUNCTION RELEASE */
@@ -34,6 +49,7 @@ __tx_free_memory_start:
3449
/* AUTHOR */
3550
/* */
3651
/* Akif Ejaz, 10xEngineers */
52+
/* Wei-Chen Lai, National Cheng Kung University */
3753
/* */
3854
/* DESCRIPTION */
3955
/* */
@@ -60,32 +76,42 @@ __tx_free_memory_start:
6076
/* _tx_initialize_kernel_enter ThreadX entry function */
6177
/* */
6278
/**************************************************************************/
79+
6380
/* VOID _tx_initialize_low_level(VOID)
6481
{ */
65-
.global _tx_initialize_low_level
66-
.weak _tx_initialize_low_level
82+
.globl _tx_initialize_low_level
6783
_tx_initialize_low_level:
68-
69-
/* Save the system stack pointer. */
70-
/* _tx_thread_system_stack_ptr = sp; */
71-
72-
la t0, _tx_thread_system_stack_ptr // Pickup address of system stack ptr
84+
la t0, _tx_thread_system_stack_ptr
7385
sw sp, 0(t0) // Save system stack pointer
7486

75-
/* Pickup first free address. */
76-
/* _tx_initialize_unused_memory(__tx_free_memory_start); */
77-
7887
la t0, __tx_free_memory_start // Pickup first free address
79-
la t1, _tx_initialize_unused_memory // Pickup address of unused memory
88+
la t1, _tx_initialize_unused_memory
8089
sw t0, 0(t1) // Save unused memory address
8190

82-
/* Initialize floating point control/status register if floating point is enabled. */
83-
#ifdef __riscv_flen
84-
li t0, 0
85-
csrw fcsr, t0 // Clear FP control/status register
91+
ret
92+
93+
94+
/* Define the actual timer interrupt/exception handler. */
95+
.globl _tx_timer_interrupt_handler
96+
.globl __minterrupt_000007
97+
_tx_timer_interrupt_handler:
98+
__minterrupt_000007:
99+
100+
/* Before calling _tx_thread_context_save, we have to allocate an interrupt
101+
stack frame and save the current value of x1 (ra). */
102+
#if defined(__riscv_32e) || defined(__riscv_32rve)
103+
addi sp, sp, -260 // Allocate space for all registers - with floating point enabled
104+
#else
105+
addi sp, sp, -128 // Allocate space for all registers - without floating point enabled
86106
#endif
107+
sw x1, 0x70(sp) // Store RA
108+
call _tx_thread_context_save // Call ThreadX context save
87109

88-
ret
110+
/* Call the ThreadX timer routine. */
111+
call _tx_timer_interrupt // Call timer interrupt handler
112+
113+
/* Timer interrupt processing is done, jump to ThreadX context restore. */
114+
tail _tx_thread_context_restore // Jump to ThreadX context restore function. Note: this does not return!
89115

90116
/* Timer Interrupt Handler Note:
91117
Platform-specific implementations must provide their own timer ISR.
@@ -109,4 +135,4 @@ _tx_initialize_low_level:
109135
110136
The port assumes Machine mode (M-mode) execution.
111137
For Supervisor mode (S-mode), use sstatus and SIE/SPIE instead of mstatus.
112-
See the RISC-V Privileged Specification for more details. */
138+
See the RISC-V Privileged Specification for more details. */

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