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Restore UVM coherence without registering Blackwell BAR1 as P2PDMA #1

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Restore UVM coherence without registering Blackwell BAR1 as P2PDMA #1

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12 changes: 12 additions & 0 deletions kernel-open/nvidia-uvm/uvm_devmem.c
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Original file line number Diff line number Diff line change
Expand Up @@ -613,6 +613,18 @@ void uvm_devmem_device_p2p_init(uvm_parent_gpu_t *parent_gpu)

parent_gpu->device_p2p_initialised = false;

if (parent_gpu->rm_info.gpuArch >= NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB100) {
// Static BAR1 is also the GPU peer aperture on non-coherent Blackwell.
// Registering it as P2PDMA memory would replace its pagemap operations
// and conflict with the BAR1-as-sysmem PTEs used for GPU peer access.
UVM_DBG_PRINT("Skipping PCI P2PDMA static BAR1 registration on non-coherent GPU %s "
"(size 0x%llx, write-combined %u)\n",
uvm_parent_gpu_name(parent_gpu),
parent_gpu->static_bar1_size,
parent_gpu->static_bar1_write_combined);
return;
}

// RM sets static_bar1_size when it has created a contiguous BAR mapping
// large enough to cover all of GPU memory that will be allocated to
// userspace buffers. This is required to support the P2PDMA feature to
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7 changes: 0 additions & 7 deletions kernel-open/nvidia-uvm/uvm_gpu.h
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Expand Up @@ -1825,13 +1825,6 @@ NvU64 uvm_parent_gpu_canonical_address(uvm_parent_gpu_t *parent_gpu, NvU64 addr)

static bool uvm_parent_gpu_is_coherent(const uvm_parent_gpu_t *parent_gpu)
{
// Blackwell+ consumer GPUs (e.g. 5090) use BAR1 P2P via the SYS_COH
// aperture rewrite in nvGpuOpsBuildExternalAllocPtes. UVM's P2P
// registration path must take the coherent route to match, otherwise
// the ZONE_DEVICE peer DMA setup conflicts with BAR1-as-sysmem PTEs.
if (parent_gpu->rm_info.gpuArch >= NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB100)
return true;

return parent_gpu->system_bus.memory_window_end > parent_gpu->system_bus.memory_window_start;
}

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