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HDLBits solutions

My Verilog solutions to HDLBits exercises, written in January 2026 while working through the site: gates and vectors, multiplexers, adders and BCD adders, Karnaugh-map problems, flip-flops, counters, edge detectors, shift registers and two small state machines. Each file is the top_module for the exercise it is named after.

These are exercise answers, not a project. Some files rely on modules or port declarations that the HDLBits problem supplies (for example count4 and bcd_fadd), so not every file compiles on its own outside the site.

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My Verilog solutions to HDLBits exercises: combinational logic, counters, shift registers, FSMs

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