FPGA Polar Code SC Decoder 📌 Project Overview This project implements a Successive Cancellation (SC) decoder for Polar codes on FPGA, focusing on low resource utilization and hardware efficiency. The design demonstrates how channel coding algorithms can be efficiently mapped onto FPGA hardware with minimal logic resources.

🧠 Background Polar codes are a class of channel codes that achieve channel capacity, widely adopted in modern communication systems such as 5G. The SC (Successive Cancellation) decoding algorithm is the most fundamental decoding method for Polar codes, offering a good trade-off between complexity and performance.

⚙️ Key Features 📉 Ultra-low resource usage LUT: 316 Flip-Flops: 192 ⚡ Hardware-efficient SC decoding architecture 🔄 Supports iterative bit-by-bit decoding 🧩 Modular design for easy extension 📊 Suitable for FPGA-based communication systems

🏗️ Architecture Overview The SC decoder is implemented based on a recursive structure, consisting of: Processing Elements (PEs) for LLR computation Partial sum update logic Control logic for sequential decoding Block RAM for LLRS storage

🚀 How to Run 1️⃣ Simulation Use your preferred simulator (e.g., ModelSim / Vivado) 2️⃣ Synthesis (Vivado) Open Vivado Add source files from src/ Run synthesis

📊 Resource Utilization Resource Usage: LUT 316 FF 192 This demonstrates the efficiency of the proposed architecture for low-cost FPGA implementations.

🔬 Design Highlights Optimized SC decoding datapath for minimal hardware usage Sequential architecture reduces parallel hardware overhead Efficient LLR computation using shared processing elements Balanced trade-off between latency and resource consumption

🚀 Future Improvements ⚡ Implement Fast-SSC decoding using specialized nodes 🧩 Introduce multiple Processing Elements (PEs) for better parallelism 🔄 Extend to SCL (Successive Cancellation List) decoding