Feature/registerfile

Makefile

@@ -7,7 +7,7 @@ CXXFLAGS += --std=c++17 -O3 -Wall -Wextra -Wshadow -Wpedantic -I./libbf/
 TRIPLET_DIR = $(patsubst %/,%,$(firstword $(filter-out $(ROOT_DIR)/vcpkg_installed/vcpkg/, $(wildcard $(ROOT_DIR)/vcpkg_installed/*/))))
 CPPFLAGS += -isystem $(TRIPLET_DIR)/include
 LDFLAGS  += -L$(TRIPLET_DIR)/lib -L$(TRIPLET_DIR)/lib/manual-link
-LDLIBS   += -llzma -lz -lbz2 -lfmt ./libbf/build/lib/libbf.a
+LDLIBS   += -llzma -lz -lbz2 -lfmt -lCLI11 ./libbf/build/lib/libbf.a
 
 .phony: all all_execs clean configclean test makedirs
 

config/instantiation_file.py

@@ -25,8 +25,9 @@
 
 core_builder_parts = {
     'ifetch_buffer_size': '.ifetch_buffer_size({ifetch_buffer_size})',
-    'decode_buffer_size': '.decode_buffer_size({dispatch_buffer_size})',
-    'dispatch_buffer_size': '.dispatch_buffer_size({decode_buffer_size})',
+    'decode_buffer_size': '.decode_buffer_size({decode_buffer_size})',
+    'dispatch_buffer_size': '.dispatch_buffer_size({dispatch_buffer_size})',
+    'register_file_size': '.register_file_size({register_file_size})',
     'rob_size': '.rob_size({rob_size})',
     'lq_size': '.lq_size({lq_size})',
     'sq_size': '.sq_size({sq_size})',

config/parse.py

@@ -72,7 +72,7 @@ def normalize_config(config_file):
 
     # Default core elements
     # Give cores numeric indices
-    core_keys_to_copy = ('frequency', 'ifetch_buffer_size', 'decode_buffer_size', 'dispatch_buffer_size', 'rob_size', 'lq_size', 'sq_size', 'fetch_width', 'decode_width', 'dispatch_width', 'execute_width', 'lq_width', 'sq_width', 'retire_width', 'mispredict_penalty', 'scheduler_size', 'decode_latency', 'dispatch_latency', 'schedule_latency', 'execute_latency', 'branch_predictor', 'btb', 'DIB')
+    core_keys_to_copy = ('frequency', 'ifetch_buffer_size', 'decode_buffer_size', 'dispatch_buffer_size', 'register_file_size', 'rob_size', 'lq_size', 'sq_size', 'fetch_width', 'decode_width', 'dispatch_width', 'execute_width', 'lq_width', 'sq_width', 'retire_width', 'mispredict_penalty', 'scheduler_size', 'decode_latency', 'dispatch_latency', 'schedule_latency', 'execute_latency', 'branch_predictor', 'btb', 'DIB')
     cores = [util.chain(cpu, util.subdict(config_file, core_keys_to_copy), {'name': 'cpu'+str(i), '_index': i}) for i,cpu in enumerate(cores)]
 
     pinned_cache_names = ('L1I', 'L1D', 'ITLB', 'DTLB', 'L2C', 'STLB')

configs/champsim_config.json

@@ -11,6 +11,7 @@
             "ifetch_buffer_size":512,
             "decode_buffer_size":128,
             "dispatch_buffer_size":128,
+            "register_file_size":128,
             "rob_size": 512,
             "lq_size": 144,
             "sq_size": 112,

inc/defaults.hpp

@@ -31,6 +31,7 @@ const auto default_core = O3_CPU::Builder{}
                               .ifetch_buffer_size(64)
                               .decode_buffer_size(32)
                               .dispatch_buffer_size(32)
+                              .register_file_size(128)
                               .rob_size(352)
                               .lq_size(128)
                               .sq_size(72)

inc/instruction.h

@@ -40,6 +40,7 @@ enum branch_type {
   NOT_BRANCH
 };
 
+using PHYSICAL_REGISTER_ID = int16_t; // signed to use -1 to indicate no physical register
 enum flags { NON_SPEC = 0, SERIAL, SERIAL_AFTER, SERIAL_BEFORE, READ_BARRIER, WRITE_BARRIER, SQUASH_AFTER, SQUASHED };
 
 struct ooo_model_instr {
@@ -83,8 +84,8 @@ struct ooo_model_instr {
   unsigned completed_mem_ops = 0;
   int num_reg_dependent = 0;
 
-  std::vector<uint8_t> destination_registers = {}; // output registers
-  std::vector<uint8_t> source_registers = {};      // input registers
+  std::vector<PHYSICAL_REGISTER_ID> destination_registers = {}; // output registers
+  std::vector<PHYSICAL_REGISTER_ID> source_registers = {};      // input registers
 
   std::vector<uint64_t> destination_memory = {};
   std::vector<uint64_t> source_memory = {};

inc/ooo_cpu.h

@@ -40,6 +40,7 @@
 #include "instruction.h"
 #include "module_impl.h"
 #include "operable.h"
+#include "register_allocator.h"
 #include "util/lru_table.h"
 #include <type_traits>
 
@@ -253,29 +254,28 @@ class O3_CPU : public champsim::operable
   std::vector<std::optional<LSQ_ENTRY>> LQ;
   std::deque<LSQ_ENTRY> SQ;
 
-  // std::array<std::vector<std::reference_wrapper<ooo_model_instr>>, std::numeric_limits<uint8_t>::max() + 1> reg_producers;
-  std::array<std::vector<ooo_model_instr*>, std::numeric_limits<uint8_t>::max() + 1> reg_producers;
-
   struct saved_instr {
     uint64_t ip = 0;
     uint64_t instr_id = 0;
     std::vector<uint64_t> source_memory = {};
-    std::vector<uint8_t> source_registers = {};
+    std::vector<PHYSICAL_REGISTER_ID> source_registers = {};
     std::vector<uint64_t> destination_memory = {};
-    std::vector<uint8_t> destination_registers = {};
+    std::vector<PHYSICAL_REGISTER_ID> destination_registers = {};
   };
 
   std::map<uint64_t, uint64_t> imap_counter;
   std::map<uint64_t, std::vector<saved_instr>> instruction_map;
 
   // Constants
-  std::size_t IFETCH_BUFFER_SIZE, DECODE_BUFFER_SIZE, DISPATCH_BUFFER_SIZE, ROB_SIZE, LQ_SIZE, SQ_SIZE;
+  std::size_t IFETCH_BUFFER_SIZE, DECODE_BUFFER_SIZE, DISPATCH_BUFFER_SIZE, REGISTER_FILE_SIZE, ROB_SIZE, LQ_SIZE, SQ_SIZE;
   long int FETCH_WIDTH, DECODE_WIDTH, DISPATCH_WIDTH, EXEC_WIDTH;
   long int LQ_WIDTH, SQ_WIDTH;
   long int RETIRE_WIDTH;
   unsigned BRANCH_MISPREDICT_PENALTY, SCHEDULER_SIZE, DECODE_LATENCY, DISPATCH_LATENCY, SCHEDULING_LATENCY, EXEC_LATENCY;
   long int L1I_BANDWIDTH, L1D_BANDWIDTH;
 
+  RegisterAllocator reg_allocator{REGISTER_FILE_SIZE};
+
   // branch
   uint64_t fetch_resume_cycle = 0;
 
@@ -388,6 +388,7 @@ class O3_CPU : public champsim::operable
     std::size_t m_ifetch_buffer_size{};
     std::size_t m_decode_buffer_size{};
     std::size_t m_dispatch_buffer_size{};
+    std::size_t m_register_file_size{};
     std::size_t m_rob_size{};
     std::size_t m_lq_size{};
     std::size_t m_sq_size{};
@@ -416,7 +417,7 @@ class O3_CPU : public champsim::operable
     template <unsigned long long OTHER_B, unsigned long long OTHER_T>
     Builder(builder_conversion_tag, const Builder<OTHER_B, OTHER_T>& other)
         : m_cpu(other.m_cpu), m_freq_scale(other.m_freq_scale), m_dib_set(other.m_dib_set), m_dib_way(other.m_dib_way), m_dib_window(other.m_dib_window),
-          m_ifetch_buffer_size(other.m_ifetch_buffer_size), m_decode_buffer_size(other.m_decode_buffer_size),
+          m_ifetch_buffer_size(other.m_ifetch_buffer_size), m_decode_buffer_size(other.m_decode_buffer_size), m_register_file_size(other.m_register_file_size),
           m_dispatch_buffer_size(other.m_dispatch_buffer_size), m_rob_size(other.m_rob_size), m_lq_size(other.m_lq_size), m_sq_size(other.m_sq_size),
           m_fetch_width(other.m_fetch_width), m_decode_width(other.m_decode_width), m_dispatch_width(other.m_dispatch_width),
           m_schedule_width(other.m_schedule_width), m_execute_width(other.m_execute_width), m_lq_width(other.m_lq_width), m_sq_width(other.m_sq_width),
@@ -469,6 +470,11 @@ class O3_CPU : public champsim::operable
       m_dispatch_buffer_size = dispatch_buffer_size_;
       return *this;
     }
+    self_type& register_file_size(std::size_t register_file_size_)
+    {
+      m_register_file_size = register_file_size_;
+      return *this;
+    }
     self_type& rob_size(std::size_t rob_size_)
     {
       m_rob_size = rob_size_;
@@ -590,7 +596,7 @@ class O3_CPU : public champsim::operable
   template <unsigned long long B_FLAG, unsigned long long T_FLAG>
   explicit O3_CPU(Builder<B_FLAG, T_FLAG> b)
       : champsim::operable(b.m_freq_scale), cpu(b.m_cpu), DIB(b.m_dib_set, b.m_dib_way, {champsim::lg2(b.m_dib_window)}, {champsim::lg2(b.m_dib_window)}),
-        LQ(b.m_lq_size), IFETCH_BUFFER_SIZE(b.m_ifetch_buffer_size), DISPATCH_BUFFER_SIZE(b.m_dispatch_buffer_size), DECODE_BUFFER_SIZE(b.m_decode_buffer_size),
+        LQ(b.m_lq_size), IFETCH_BUFFER_SIZE(b.m_ifetch_buffer_size), DISPATCH_BUFFER_SIZE(b.m_dispatch_buffer_size), DECODE_BUFFER_SIZE(b.m_decode_buffer_size), REGISTER_FILE_SIZE(b.m_register_file_size),
         ROB_SIZE(b.m_rob_size), LQ_SIZE(b.m_lq_size), SQ_SIZE(b.m_sq_size), FETCH_WIDTH(b.m_fetch_width), DECODE_WIDTH(b.m_decode_width), DISPATCH_WIDTH(b.m_dispatch_width),
         SCHEDULER_SIZE(b.m_schedule_width), EXEC_WIDTH(b.m_execute_width), LQ_WIDTH(b.m_lq_width), SQ_WIDTH(b.m_sq_width), RETIRE_WIDTH(b.m_retire_width),
         BRANCH_MISPREDICT_PENALTY(b.m_mispredict_penalty), DISPATCH_LATENCY(b.m_dispatch_latency), DECODE_LATENCY(b.m_decode_latency),

inc/options.h

@@ -15,6 +15,7 @@ class Options
   std::size_t decode_buffer_size;
   std::size_t dispatch_buffer_size;
   std::size_t rob_size;
+  std::size_t register_file_size;
   std::size_t lq_size;
   std::size_t sq_size;
 
@@ -48,4 +49,4 @@ class Options
 
 } // namespace champsim
 
-#endif
+#endif

inc/register_allocator.h

@@ -0,0 +1,46 @@
+#include <array>
+#include <cstdint>
+#include <list>
+#include <optional>
+#include <queue>
+#include <fmt/core.h>
+#include <fmt/format.h>
+
+#ifndef REG_ALLOC_H
+#define REG_ALLOC_H
+
+#include "instruction.h"
+
+struct physical_register {
+  uint16_t arch_reg_index;
+  uint64_t producing_instruction_id;
+  bool valid; // has the producing instruction committed yet?
+  bool busy;  // is this register in use anywhere in the pipeline?
+};
+
+class RegisterAllocator
+{
+private:
+  std::array<PHYSICAL_REGISTER_ID, std::numeric_limits<uint8_t>::max() + 1> frontend_RAT, backend_RAT, snapshot_frontend_RAT;
+  std::queue<PHYSICAL_REGISTER_ID> free_registers;
+  std::vector<PHYSICAL_REGISTER_ID> wp_issued_registers;
+  std::vector<physical_register> physical_register_file;
+  bool in_wp = false;
+
+public:
+  RegisterAllocator(size_t num_physical_registers);
+  PHYSICAL_REGISTER_ID rename_dest_register(int16_t reg, uint64_t producer_id);
+  PHYSICAL_REGISTER_ID rename_src_register(int16_t reg);
+  void complete_dest_register(PHYSICAL_REGISTER_ID physreg);
+  void retire_dest_register(PHYSICAL_REGISTER_ID physreg);
+  void free_register(PHYSICAL_REGISTER_ID physreg);
+  bool isValid(PHYSICAL_REGISTER_ID physreg) const;
+  bool isAllocated(PHYSICAL_REGISTER_ID archreg) const;
+  unsigned long count_free_registers() const;
+  int count_reg_dependencies(const ooo_model_instr& instr) const;
+  void save_frontend_RAT();
+  void restore_frontend_RAT();
+  bool inWrongPath() const;
+  void print_deadlock();
+};
+#endif