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Silicon Dreams — Verilog Project Template

This is the Tiny Tapeout project template used by Silicon Dreams (CM-HW-101), a three-week co-delivered course from ChipMango and ChipFoundry that takes learners from RTL to real silicon. It's built on the same open-source pillars Tiny Tapeout uses — the SkyWater SKY130 PDK, the OpenLane/LibreLane digital flow, and the fixed Tiny Tapeout pad interface — so the Verilog you write here is genuinely synthesised, verified, and submitted to a real multi-project wafer shuttle.

What is Tiny Tapeout?

Tiny Tapeout is an educational project that aims to make it easier and cheaper than ever to get your digital and analog designs manufactured on a real chip.

To learn more and get started, visit https://tinytapeout.com.

What is Silicon Dreams?

Silicon Dreams wraps that same tapeout pipeline in a course narrative: you're an independent hardware contractor commissioned to replace the relay-logic elevator controller in a nine-floor building, Mango Tower. Across three modules you design the controller's FSM, harden it against a fault-injection gauntlet, and finally ship a hardened multi-module design to the shuttle. Learn more at chipmango.io/silicon-dreams.

Set up your Verilog project

  1. Add your Verilog files to the src folder.
  2. Edit info.yaml and update information about your project, paying special attention to the source_files and top_module properties. If you are upgrading an existing Tiny Tapeout project, check out the online info.yaml migration tool.
  3. Edit docs/info.md and add a description of your project.
  4. Adapt the testbench to your design. See test/README.md for more information.

The GitHub action will automatically build the ASIC files using LibreLane.

Enable GitHub Actions to build the results page

Resources

What next?


ChipMango × ChipFoundry · MoU Partnership 2026 · CM-HW-101

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