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Merged
alexcrichton merged 1 commit into from
Jul 23, 2026
+1,111 −16
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winch(aarch64) v128 int arith #13928

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51 changes: 51 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/f32x4_add.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(f32x4.add
(v128.const f32x4 1.5 2.5 -3.25 100)
(v128.const f32x4 0.25 -0.5 3.25 0.125)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x90
;; fadd v1.4s, v1.4s, v0.4s
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: .byte 0x00, 0x00, 0x80, 0x3e
;; 84: .byte 0x00, 0x00, 0x00, 0xbf
;; 88: .byte 0x00, 0x00, 0x50, 0x40
;; 8c: .byte 0x00, 0x00, 0x00, 0x3e
;; 90: .byte 0x00, 0x00, 0xc0, 0x3f
;; 94: .byte 0x00, 0x00, 0x20, 0x40
;; 98: .byte 0x00, 0x00, 0x50, 0xc0
;; 9c: .byte 0x00, 0x00, 0xc8, 0x42
51 changes: 51 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/f32x4_sub.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(f32x4.sub
(v128.const f32x4 1.5 2.5 -3.25 100)
(v128.const f32x4 0.25 -0.5 3.25 0.125)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x90
;; fsub v1.4s, v1.4s, v0.4s
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: .byte 0x00, 0x00, 0x80, 0x3e
;; 84: .byte 0x00, 0x00, 0x00, 0xbf
;; 88: .byte 0x00, 0x00, 0x50, 0x40
;; 8c: .byte 0x00, 0x00, 0x00, 0x3e
;; 90: .byte 0x00, 0x00, 0xc0, 0x3f
;; 94: .byte 0x00, 0x00, 0x20, 0x40
;; 98: .byte 0x00, 0x00, 0x50, 0xc0
;; 9c: .byte 0x00, 0x00, 0xc8, 0x42
51 changes: 51 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/f64x2_add.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(f64x2.add
(v128.const f64x2 1.5 -2.25)
(v128.const f64x2 0.75 2.5)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x90
;; fadd v1.2d, v1.2d, v0.2d
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: udf #0
;; 84: .byte 0x00, 0x00, 0xe8, 0x3f
;; 88: udf #0
;; 8c: .byte 0x00, 0x00, 0x04, 0x40
;; 90: udf #0
;; 94: .byte 0x00, 0x00, 0xf8, 0x3f
;; 98: udf #0
;; 9c: mov z0.b, p0/m, za0h.b[w12, 0]
51 changes: 51 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/f64x2_sub.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(f64x2.sub
(v128.const f64x2 1.5 -2.25)
(v128.const f64x2 0.75 2.5)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x90
;; fsub v1.2d, v1.2d, v0.2d
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: udf #0
;; 84: .byte 0x00, 0x00, 0xe8, 0x3f
;; 88: udf #0
;; 8c: .byte 0x00, 0x00, 0x04, 0x40
;; 90: udf #0
;; 94: .byte 0x00, 0x00, 0xf8, 0x3f
;; 98: udf #0
;; 9c: mov z0.b, p0/m, za0h.b[w12, 0]
51 changes: 51 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i16x8_add.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i16x8.add
(v128.const i16x8 100 200 300 400 500 600 700 800)
(v128.const i16x8 1 2 3 4 5 6 7 8)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x90
;; add v1.8h, v1.8h, v0.8h
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: .byte 0x01, 0x00, 0x02, 0x00
;; 84: .byte 0x03, 0x00, 0x04, 0x00
;; 88: .byte 0x05, 0x00, 0x06, 0x00
;; 8c: .byte 0x07, 0x00, 0x08, 0x00
;; 90: .byte 0x64, 0x00, 0xc8, 0x00
;; 94: .byte 0x2c, 0x01, 0x90, 0x01
;; 98: .byte 0xf4, 0x01, 0x58, 0x02
;; 9c: .byte 0xbc, 0x02, 0x20, 0x03
51 changes: 51 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i16x8_add_sat_s.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i16x8.add_sat_s
(v128.const i16x8 32767 -32768 1000 -1000 0 1 32767 -1)
(v128.const i16x8 1 -1 1000 -1000 0 1 -1 32767)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x90
;; sqadd v1.8h, v1.8h, v0.8h
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: .byte 0x01, 0x00, 0xff, 0xff
;; 84: stur d8, [sp, #-0x80]
;; 88: .byte 0x00, 0x00, 0x01, 0x00
;; 8c: .byte 0xff, 0xff, 0xff, 0x7f
;; 90: .byte 0xff, 0x7f, 0x00, 0x80
;; 94: stur d8, [sp, #-0x80]
;; 98: .byte 0x00, 0x00, 0x01, 0x00
;; 9c: .byte 0xff, 0x7f, 0xff, 0xff
51 changes: 51 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i16x8_add_sat_u.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i16x8.add_sat_u
(v128.const i16x8 65535 60000 1000 0 1 32768 65535 2)
(v128.const i16x8 1 10000 1000 0 1 32768 0 65535)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x90
;; uqadd v1.8h, v1.8h, v0.8h
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: .byte 0x01, 0x00, 0x10, 0x27
;; 84: udf #0x3e8
;; 88: .byte 0x01, 0x00, 0x00, 0x80
;; 8c: .byte 0x00, 0x00, 0xff, 0xff
;; 90: bics xzr, xzr, x0, lsr #63
;; 94: udf #0x3e8
;; 98: .byte 0x01, 0x00, 0x00, 0x80
;; 9c: .byte 0xff, 0xff, 0x02, 0x00
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