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Merged
alexcrichton merged 1 commit into from
Jul 23, 2026
Merged

winch(aarch64): add v128 bitwise ops #13921

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6 changes: 4 additions & 2 deletions crates/test-util/src/wast.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -513,7 +513,10 @@ impl WastTest {
}

if config.compiler == Compiler::Winch && cfg!(target_arch = "aarch64") {
let now_supported = ["misc_testsuite/winch/v128_load_lane_invalid_address.wast"];
let now_supported = [
"misc_testsuite/winch/v128_load_lane_invalid_address.wast",
"misc_testsuite/simd/issue4807.wast",
];
if now_supported.iter().any(|part| self.path.ends_with(part)) {
return false;
}
Expand Down Expand Up @@ -557,7 +560,6 @@ impl WastTest {
"misc_testsuite/simd/cvt-from-uint.wast",
"misc_testsuite/simd/edge-of-memory.wast",
"misc_testsuite/simd/interesting-float-splat.wast",
"misc_testsuite/simd/issue4807.wast",
"misc_testsuite/simd/issue6725-no-egraph-panic.wast",
"misc_testsuite/simd/issue_3173_select_v128.wast",
"misc_testsuite/simd/issue_3327_bnot_lowering.wast",
Expand Down
51 changes: 51 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/and.wat
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@@ -0,0 +1,51 @@
;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(v128.and
(v128.const i64x2 0 -1)
(v128.const i64x2 -1 0)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x90
;; and v1.16b, v1.16b, v0.16b
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: .byte 0xff, 0xff, 0xff, 0xff
;; 84: .byte 0xff, 0xff, 0xff, 0xff
;; 88: udf #0
;; 8c: udf #0
;; 90: udf #0
;; 94: udf #0
;; 98: .byte 0xff, 0xff, 0xff, 0xff
;; 9c: .byte 0xff, 0xff, 0xff, 0xff
51 changes: 51 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/andnot.wat
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@@ -0,0 +1,51 @@
;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(v128.andnot
(v128.const i64x2 0 -1)
(v128.const i64x2 -1 0)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x90
;; bic v1.16b, v1.16b, v0.16b
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: .byte 0xff, 0xff, 0xff, 0xff
;; 84: .byte 0xff, 0xff, 0xff, 0xff
;; 88: udf #0
;; 8c: udf #0
;; 90: udf #0
;; 94: udf #0
;; 98: .byte 0xff, 0xff, 0xff, 0xff
;; 9c: .byte 0xff, 0xff, 0xff, 0xff
39 changes: 39 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/any_true.wat
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@@ -0,0 +1,39 @@
;;! target = "aarch64"
;;! test = "winch"

(module
(func (export "run") (result i32)
(v128.any_true (v128.const i64x2 0 1))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x6c
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x70
;; umaxp v31.4s, v0.4s, v0.4s
;; mov x0, v31.d[0]
;; cmp x0, #0
;; cset x0, ne
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 6c: udf #0xc11f
;; 70: udf #0
;; 74: udf #0
;; 78: udf #1
;; 7c: udf #0
56 changes: 56 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/bitselect.wat
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@@ -0,0 +1,56 @@
;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(v128.bitselect
(v128.const i64x2 1 2)
(v128.const i64x2 3 4)
(v128.const i64x2 -1 0)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x7c
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x90
;; ldr q2, #0xa0
;; mov v3.16b, v0.16b
;; bsl v3.16b, v2.16b, v1.16b
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q3, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 7c: udf #0xc11f
;; 80: .byte 0xff, 0xff, 0xff, 0xff
;; 84: .byte 0xff, 0xff, 0xff, 0xff
;; 88: udf #0
;; 8c: udf #0
;; 90: udf #3
;; 94: udf #0
;; 98: udf #4
;; 9c: udf #0
;; a0: udf #1
;; a4: udf #0
;; a8: udf #2
;; ac: udf #0
45 changes: 45 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/not.wat
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@@ -0,0 +1,45 @@
;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(v128.not (v128.const i32x4 1 2 3 4)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x70
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; mvn v0.16b, v0.16b
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q0, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 70: udf #0xc11f
;; 74: udf #0
;; 78: udf #0
;; 7c: udf #0
;; 80: udf #1
;; 84: udf #2
;; 88: udf #3
;; 8c: udf #4
51 changes: 51 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/or.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(v128.or
(v128.const i64x2 0 -1)
(v128.const i64x2 -1 0)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x90
;; orr v1.16b, v0.16b, v1.16b
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: .byte 0xff, 0xff, 0xff, 0xff
;; 84: .byte 0xff, 0xff, 0xff, 0xff
;; 88: udf #0
;; 8c: udf #0
;; 90: udf #0
;; 94: udf #0
;; 98: .byte 0xff, 0xff, 0xff, 0xff
;; 9c: .byte 0xff, 0xff, 0xff, 0xff
51 changes: 51 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/xor.wat
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@@ -0,0 +1,51 @@
;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(v128.xor
(v128.const i64x2 0 -1)
(v128.const i64x2 -1 0)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x90
;; eor v1.16b, v0.16b, v1.16b
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: .byte 0xff, 0xff, 0xff, 0xff
;; 84: .byte 0xff, 0xff, 0xff, 0xff
;; 88: udf #0
;; 8c: udf #0
;; 90: udf #0
;; 94: udf #0
;; 98: .byte 0xff, 0xff, 0xff, 0xff
;; 9c: .byte 0xff, 0xff, 0xff, 0xff
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