winch(aarch64): add v128.const support

crates/test-util/src/wast.rs

@@ -512,6 +512,13 @@ impl WastTest {
             }
         }
 
+        if config.compiler == Compiler::Winch && cfg!(target_arch = "aarch64") {
+            let now_supported = ["misc_testsuite/winch/v128_load_lane_invalid_address.wast"];
+            if now_supported.iter().any(|part| self.path.ends_with(part)) {
+                return false;
+            }
+        }
+
         if config.compiler.should_fail(&self.config) {
             return true;
         }
@@ -565,7 +572,6 @@ impl WastTest {
                     "misc_testsuite/winch/issue-10460.wast",
                     "misc_testsuite/winch/replace_lane.wast",
                     "misc_testsuite/winch/simd_multivalue.wast",
-                    "misc_testsuite/winch/v128_load_lane_invalid_address.wast",
                     "spec_testsuite/proposals/annotations/simd_lane.wast",
                     "spec_testsuite/proposals/multi-memory/simd_memory-multi.wast",
                     "spec_testsuite/simd_address.wast",

tests/disas/winch/aarch64/v128_const/const.wat

@@ -0,0 +1,40 @@
+;;! target = "aarch64"
+;;! test = "winch"
+
+(module
+  (memory 1)
+  (func (export "run")
+    (v128.store (i32.const 0) (v128.const i32x4 1 2 3 4))))
+;; wasm[0]::function[0]:
+;;       stp     x29, x30, [sp, #-0x10]!
+;;       mov     x29, sp
+;;       str     x28, [sp, #-0x10]!
+;;       mov     x28, sp
+;;       ldur    x16, [x0, #8]
+;;       ldur    x16, [x16, #0x18]
+;;       mov     x17, #0
+;;       movk    x17, #0x10
+;;       add     x16, x16, x17
+;;       cmp     sp, x16
+;;       b.lo    #0x6c
+;;   2c: mov     x9, x0
+;;       sub     x28, x28, #0x10
+;;       mov     sp, x28
+;;       stur    x0, [x28, #8]
+;;       stur    x1, [x28]
+;;       ldr     q0, #0x70
+;;       mov     x0, #0
+;;       ldur    x1, [x9, #0x38]
+;;       add     x1, x1, w0, uxtw
+;;       stur    q0, [x1]
+;;       add     x28, x28, #0x10
+;;       mov     sp, x28
+;;       mov     sp, x28
+;;       ldr     x28, [sp], #0x10
+;;       ldp     x29, x30, [sp], #0x10
+;;       ret
+;;   6c: udf     #0xc11f
+;;   70: udf     #1
+;;   74: udf     #2
+;;   78: udf     #3
+;;   7c: udf     #4

winch/codegen/src/codegen/error.rs

@@ -35,9 +35,6 @@ pub(crate) enum CodeGenError {
     /// Unsupported eager initialization of tables.
     #[error("Unsupported eager initialization of tables")]
     UnsupportedTableEagerInit,
-    /// Unsupported immediate for instruction.
-    #[error("Unsupported immediate")]
-    UnsupportedImm,
     /// An internal error.
     ///
     /// This error means that an internal invariant was not met and usually
@@ -179,10 +176,6 @@ impl CodeGenError {
         Self::Internal(InternalError::InvalidLocalOffset)
     }
 
-    pub(crate) const fn unsupported_imm() -> Self {
-        Self::UnsupportedImm
-    }
-
     pub(crate) const fn invalid_two_arg_form() -> Self {
         Self::Internal(InternalError::InvalidTwoArgumentForm)
     }

winch/codegen/src/isa/aarch64/asm.rs

@@ -313,7 +313,11 @@ impl Assembler {
                     .for_each(|i| self.emit(i));
             }
             RegClass::Float => {
-                match ASIMDFPModImm::maybe_from_u64(imm.unwrap_as_u64(), size.into()) {
+                let modimm = match imm {
+                    Imm::V128(_) => None,
+                    _ => ASIMDFPModImm::maybe_from_u64(imm.unwrap_as_u64(), size.into()),
+                };
+                match modimm {
                     Some(imm) => {
                         self.emit(Inst::FpuMoveFPImm {
                             rd: rd.map(Into::into),

winch/codegen/src/isa/aarch64/masm.rs

@@ -6,7 +6,7 @@ use super::{
     regs::{self, scratch_fpr_bitset, scratch_gpr_bitset},
 };
 use crate::{
-    Context, Result,
+    Result,
     abi::{self, align_to, calculate_frame_adjustment, local::LocalSlot, vmctx},
     bail,
     codegen::{CodeGenContext, CodeGenError, Emission, FuncEnv, ptr_type_from_ptr_size},
@@ -517,14 +517,10 @@ impl Masm for MacroAssembler {
                     self.asm.mov_ir(dst, v, v.size());
                     Ok(())
                 }
-                imm @ (I::F32(_) | I::F64(_)) => {
+                imm @ (I::F32(_) | I::F64(_) | I::V128(_)) => {
                     self.asm.mov_ir(dst, imm, imm.size());
                     Ok(())
                 }
-                I::V128(_) => Err(CodeGenError::unsupported_imm()).context(
-                    "v128 immediates are not supported in winch+aarch64; the SIMD and \
-                     relaxed-SIMD proposals are unimplemented for this target",
-                ),
             },
             (RegImm::Reg(rs), rd) => match (rs.class(), rd.to_reg().class()) {
                 (RegClass::Int, RegClass::Int) => Ok(self.asm.mov_rr(rs, rd, size)),