Make the dead-load-with-context instruction a MachInst at root.

This gives us a place to put regalloc constraints and to gather metadata (specifically, instruction locations).

Add a compile disas test to make sure `dead_load_with_context` is still emitting an acceptable dead load. It is. The only difference is that it's loading into `rdx` rather than `edx` now, probably due to my new regalloc constraints:

```
-      movl    (%rdx), %edx
+      movq    (%rdx), %rdx
```

Also...
* Make the new instruction a `.call()` in consistency with `stack_switch` being one.
* Move the RDI-specificity to the regalloc constraints, which lets us remove the preg_rdi ISLE constructor I had added.
* Reserve r10 as a scratch register.

Author: erikrose

cranelift/codegen/meta/src/shared/instructions.rs

@@ -395,6 +395,8 @@ fn define_control_flow(
         ``VMContext``'s ``vm_store_context``) and can use the second
         reserved register to store a temp value, as needed on platforms
         where signal handlers cannot push stack frames.
+
+        On x64, RDI holds ``context``, and R10 is used as scratch space.
         "#,
             &formats.binary,
         )
@@ -403,8 +405,10 @@ fn define_control_flow(
             Operand::new("context", iAddr)
                 .with_doc("arbitrary address-sized context to pass to signal handler"),
         ])
-        // Are we a call? stack_switch calls itself one "as it continues execution elsewhere".
-        // .is_call()
+        // Are we a call? stack_switch calls itself one "as it continues
+        // execution elsewhere". See reasoning at
+        // https://github.com/bytecodealliance/wasmtime/pull/9078#issuecomment-2273869774.
+        .call()
         .can_load()
         // Don't optimize me out just because I don't def anything. TODO: Can we use side_effects_idempotent()?
         .other_side_effects(),

cranelift/codegen/src/ir/instructions.rs

@@ -613,9 +613,13 @@ impl InstructionData {
             Self::Ternary {
                 opcode: Opcode::StackSwitch,
                 ..
+            }
+            | Self::Binary {
+                opcode: Opcode::DeadLoadWithContext,
+                ..
             } => {
-                // `StackSwitch` is not actually a call, but has the .call() side
-                // effect as it continues execution elsewhere.
+                // These instructions aren't actually calls, but they have the
+                // .call() side effect, as they continue execution elsewhere.
                 CallInfo::NotACall
             }
             _ => {

cranelift/codegen/src/isa/x64/inst.isle

@@ -194,6 +194,9 @@
                     (offset i64)
                     (distance RelocDistance))
 
+       (DeadLoadWithContext (load_ptr Gpr)
+                            (context Gpr))
+
        ;; =========================================
        ;; Instructions pertaining to atomic memory accesses.
 
@@ -1342,6 +1345,12 @@
 (rule (return_call_unknown info)
       (SideEffectNoResult.Inst (MInst.ReturnCallUnknown info)))
 
+;; Helper for creating `DeadLoadWithContext` instructions.
+(decl x64_dead_load_with_context (Gpr Gpr) SideEffectNoResult)
+(rule (x64_dead_load_with_context load_ptr context)
+      (SideEffectNoResult.Inst (MInst.DeadLoadWithContext load_ptr
+                                                          context)))
+
 ;;;; Helpers for emitting stack switches ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (decl x64_stack_switch_basic (Gpr Gpr Gpr) Gpr)
@@ -4064,9 +4073,6 @@
 (decl preg_rsp () PReg)
 (extern constructor preg_rsp preg_rsp)
 
-(decl preg_rdi () PReg)
-(extern constructor preg_rdi preg_rdi)
-
 (decl preg_pinned () PReg)
 (extern constructor preg_pinned preg_pinned)
 

cranelift/codegen/src/isa/x64/inst/emit.rs

@@ -645,6 +645,14 @@ pub(crate) fn emit(
             sink.bind_label(resume, state.ctrl_plane_mut());
         }
 
+        Inst::DeadLoadWithContext { .. } => {
+            // The ISLE has already emitted the dead load. Put the address of
+            // this instruction aside so we can later distinguish whether a
+            // segfault is its fault.
+
+            // Search for "let pc_offset = layout.ip_offset as i32;" as a string to pull on.
+        }
+
         Inst::JmpKnown { dst } => uncond_jmp(sink, *dst),
 
         Inst::WinchJmpIf { cc, taken } => one_way_jmp(sink, *cc, *taken),

cranelift/codegen/src/isa/x64/inst/mod.rs

@@ -1,6 +1,7 @@
 //! This module defines x86_64-specific machine instruction types.
 
 pub use emit_state::EmitState;
+use regalloc2::PRegSet;
 
 use crate::binemit::{Addend, CodeOffset, Reloc};
 use crate::ir::{ExternalName, LibCall, TrapCode, Type, types};
@@ -96,6 +97,7 @@ impl Inst {
             | Inst::Args { .. }
             | Inst::Rets { .. }
             | Inst::StackSwitchBasic { .. }
+            | Inst::DeadLoadWithContext { .. }
             | Inst::TrapIf { .. }
             | Inst::TrapIfAnd { .. }
             | Inst::TrapIfOr { .. }
@@ -671,6 +673,12 @@ impl PrettyPrint for Inst {
                 )
             }
 
+            Inst::DeadLoadWithContext { load_ptr, context } => {
+                let load_ptr = pretty_print_reg(**load_ptr, 8);
+                let context = pretty_print_reg(**context, 8);
+                format!("dead_load_with_context {load_ptr}, {context}")
+            }
+
             Inst::JmpKnown { dst } => {
                 let op = ljustify("jmp".to_string());
                 let dst = dst.to_string();
@@ -1045,6 +1053,19 @@ fn x64_get_operands(inst: &mut Inst, collector: &mut impl OperandVisitor) {
             collector.reg_clobbers(clobbers);
         }
 
+        Inst::DeadLoadWithContext { load_ptr, context } => {
+            // load_ptr is an input param.
+            collector.reg_use(load_ptr);
+            // Demand context (vmctx) go into RDI.
+            // TODO: Do I still have to move it, or will regalloc make sure it's there?
+            collector.reg_fixed_use(context, regs::rdi());
+            // Reserve r10 as a place for the signal handler to stow the return
+            // address (which we're overwriting with that of the epoch-ending
+            // stub). Picking r10 because it's caller-saved but otherwise
+            // arbitrarily.
+            collector.reg_clobbers(PRegSet::empty().with(regs::gpr_preg(asm::gpr::enc::R10)));
+        }
+
         Inst::ReturnCallKnown { info } => {
             let ReturnCallInfo {
                 dest, uses, tmp, ..

cranelift/codegen/src/isa/x64/lower.isle

@@ -3583,10 +3583,16 @@
 (rule (lower (dead_load_with_context load_ptr context))
       (let (
             ;; Put vmctx into rdi. TODO: Do we have to shove context in a different reg first? The type system seems happy to allow it without.
-            (_ SideEffectNoResult (mov_to_preg (preg_rdi) context))
+            ;; Actually, I suspect we don't even need to do this move; because we use reg_fixed_use() to constrain the `context` arg of DeadLoadWithContext to RDI, I hypothesize regalloc will insert any MOV needed to make that so. It is, after all, in the business of inserting MOVs for spills.
+            ;; (_ SideEffectNoResult (mov_to_preg (preg_rdi) context))
+
             ;; Load from load_ptr to perhaps trigger a trap.
             ;; TODO: May be able to change x64_load to higher-level "load", from codegen/meta/src/shared/instructions.rs.
-            (_ Gpr (x64_load $I64 (to_amode (mem_flags_aligned_read_only) load_ptr (zero_offset)) (ExtKind.None))))
+            (_ Gpr (x64_load $I64 (to_amode (mem_flags_aligned_read_only)
+                                             load_ptr
+                                             (zero_offset))
+                                  (ExtKind.None)))
+            (_ SideEffectNoResult (x64_dead_load_with_context load_ptr context)))
        (output_none)))
 
 ;;;; Rules for `get_{frame,stack}_pointer` and `get_return_address` ;;;;;;;;;;;;

cranelift/codegen/src/isa/x64/lower/isle.rs

@@ -658,11 +658,6 @@ impl Context for IsleContext<'_, '_, MInst, X64Backend> {
         regs::rsp().to_real_reg().unwrap().into()
     }
 
-    #[inline]
-    fn preg_rdi(&mut self) -> PReg {
-        regs::rdi().to_real_reg().unwrap().into()
-    }
-
     #[inline]
     fn preg_pinned(&mut self) -> PReg {
         regs::pinned_reg().to_real_reg().unwrap().into()

cranelift/codegen/src/isa/x64/pcc.rs

@@ -209,6 +209,8 @@ pub(crate) fn check(
 
         Inst::StackSwitchBasic { .. } => Err(PccError::UnimplementedInst),
 
+        Inst::DeadLoadWithContext { .. } => Err(PccError::UnimplementedInst),
+
         Inst::LabelAddress { .. } => Err(PccError::UnimplementedInst),
 
         Inst::SequencePoint { .. } => Ok(()),

cranelift/interpreter/src/step.rs

@@ -1316,6 +1316,7 @@ where
         Opcode::X86Pmaddubsw => unimplemented!("X86Pmaddubsw"),
         Opcode::X86Cvtt2dq => unimplemented!("X86Cvtt2dq"),
         Opcode::StackSwitch => unimplemented!("StackSwitch"),
+        Opcode::DeadLoadWithContext => unimplemented!("DeadLoadWithContext"),
 
         Opcode::TryCall => unimplemented!("TryCall"),
         Opcode::TryCallIndirect => unimplemented!("TryCallIndirect"),

tests/disas/epoch-interruption-mmu-compile.wat

@@ -0,0 +1,17 @@
+;;! target = "x86_64"
+;;! test = "compile"
+;;! flags = ["-Wepoch-interruption-via-mmu=y"]
+
+(module
+  (memory 0)
+  (func)
+)
+;; wasm[0]::function[0]:
+;;       pushq   %rbp
+;;       movq    %rsp, %rbp
+;;       movq    8(%rdi), %rdx
+;;       movq    0x10(%rdx), %rdx
+;;       movq    (%rdx), %rdx
+;;       movq    %rbp, %rsp
+;;       popq    %rbp
+;;       retq