feat(cpu): ARM64 NEON GEMM micro-kernel and element-wise ops (#106) - #152
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Phase 1: 4×8 register-blocked GEMM micro-kernel using VFMLA/VLD1/VLD1R/VST1 Plan 9 mnemonics. 8 accumulator V-registers, packed A/B panels matching the amd64 AVX2 GEMM pattern. gemmMr=4, gemmNr=8. Runtime dispatch via HasASIMD. Phase 2: Element-wise Add/Sub/Mul/Div float32 using WORD-encoded FADD/FSUB/ FMUL/FDIV (.4S vectors). Scalar tail for remainder. All 8 kernels wired into existing simd function pointers. simdMinLen=32 threshold applies. Cross-compile verified: arm64/linux, arm64/darwin, amd64, wasm. 34 GEMM test shapes + dispatch + allocs + benchmark. Lint: 0 issues.
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This was referenced Aug 4, 2026
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Summary
ARM64 NEON SIMD support — GEMM micro-kernel and element-wise float32 operations.
Phase 1: GEMM micro-kernel (Plan 9 mnemonics)
gemmMicroKernel4x8NEON): 8 accumulator V-registers, VFMLA inner loop, packed A/B panels. Mirrors the amd64 AVX2 6×16 kernel pattern.gemmMicroKernel1x8NEON): for row tail and GEMV shapes.cpu.ARM64.HasASIMD(mandatory on all arm64 hardware).Phase 2: Element-wise ops (WORD encoding)
simdXxxFloat32function pointers withsimdMinLen=32thresholdFiles
gemm_microkernel_arm64.s— 152 lines Plan 9 assemblygemm_microkernel_stub_arm64.go— Go declarationsmatmul_gemm_arm64.go— dispatch + packing (197 lines)matmul_gemm_arm64_test.go— 34 shapes + dispatch + allocs + benchmarksimd_neon_arm64.s— 352 lines (8 kernels)simd_neon_stub_arm64.go— Go declarationssimd_neon_arm64.go— init() registrationmatmul_gemm.go— gemmMinCols → var (8 for arm64, 16 for amd64)Test plan
go build ./...(amd64)GOARCH=arm64 GOOS=linux go build ./...GOARCH=arm64 GOOS=darwin go build ./...GOOS=js GOARCH=wasm go build ./...go vet ./...gofmt— cleangolangci-lint run— 0 issuesgo test -short ./...— 22/22 pass, 0 failuresCloses #106