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[DEBUG]: iommu/arm-smmu: Track s2cr values in arm-smmu QCOM implement… #1

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[DEBUG]: iommu/arm-smmu: Track s2cr values in arm-smmu QCOM implement… #1

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f77bb86
FROMLIST arm64: dts: qcom: kodiak: Add GEM_NOC interconnect for adren…
bibekpatro May 26, 2026
aadf018
FROMLIST: arm64: dts: qcom: lemans: Add GEM_NOC interconnect for adre…
bibekpatro May 26, 2026
e385daa
FROMLIST: arm64: dts: qcom: monaco: Add GEM_NOC interconnect for adre…
bibekpatro May 26, 2026
910e433
FROMLIST: arm64: dts: qcom: talos: Add GEM_NOC interconnect for adren…
bibekpatro May 26, 2026
2be7e45
[DEBUG]: iommu/arm-smmu: Track s2cr values in arm-smmu QCOM implement…
bibekpatro May 30, 2026
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2 changes: 2 additions & 0 deletions arch/arm64/boot/dts/qcom/lemans.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -4427,6 +4427,8 @@
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
};

serdes0: phy@8901000 {
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2 changes: 2 additions & 0 deletions arch/arm64/boot/dts/qcom/monaco.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -4977,6 +4977,8 @@
"gpu_cc_hub_aon_clk";
power-domains = <&gpucc GPU_CC_CX_GDSC>;
dma-coherent;
interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
};

pmu@9091000 {
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2 changes: 2 additions & 0 deletions arch/arm64/boot/dts/qcom/sc7280.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -3333,6 +3333,8 @@

power-domains = <&gpucc GPU_CC_CX_GDSC>;
dma-coherent;
interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
};

gfx_0_tbu: tbu@3dd9000 {
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2 changes: 2 additions & 0 deletions arch/arm64/boot/dts/qcom/talos.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -2133,6 +2133,8 @@
"iface";
power-domains = <&gpucc CX_GDSC>;
dma-coherent;
interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
};

stm@6002000 {
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28 changes: 28 additions & 0 deletions drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
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Original file line number Diff line number Diff line change
Expand Up @@ -541,6 +541,15 @@ static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
u32 type = s2cr->type;
u32 reg;

dev_info(smmu->dev,
"write_s2cr[%d]: smmu_base=0x%llx orig type=%u cbndx=%u privcfg=%u%s\n",
idx, (u64)smmu->ioaddr, type, cbndx, s2cr->privcfg,
smmu->smrs && smmu->smrs[idx].valid ?
" (SMR valid)" : "");
if (smmu->smrs && smmu->smrs[idx].valid)
dev_err(smmu->dev, "write_s2cr[%d]: SMR id=0x%x mask=0x%x\n",
idx, smmu->smrs[idx].id, smmu->smrs[idx].mask);

if (qsmmu->bypass_quirk) {
if (type == S2CR_TYPE_BYPASS) {
/*
Expand All @@ -551,6 +560,9 @@ static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
*/
type = S2CR_TYPE_TRANS;
cbndx = qsmmu->bypass_cbndx;
dev_info(smmu->dev,
"write_s2cr[%d]: bypass_quirk: BYPASS->TRANS cbndx=%u\n",
idx, cbndx);
} else if (type == S2CR_TYPE_FAULT) {
/*
* Firmware with quirky S2CR handling will ignore FAULT
Expand All @@ -559,13 +571,29 @@ static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
*/
type = S2CR_TYPE_BYPASS;
cbndx = 0xff;
dev_info(smmu->dev,
"write_s2cr[%d]: bypass_quirk: FAULT->BYPASS cbndx=0xff\n",
idx);
}
}

reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) |
FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) |
FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg);

dev_err(smmu->dev,
"write_s2cr[%d]: off=0x%x phys=0x%llx val=0x%08x (type=%u cbndx=%u privcfg=%u)\n",
idx, ARM_SMMU_GR0_S2CR(idx),
(u64)smmu->ioaddr + ARM_SMMU_GR0_S2CR(idx),
reg, type, cbndx, s2cr->privcfg);

arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);

dev_err(smmu->dev,
"read_s2cr[%d]: off=0x%x phys=0x%llx val=0x%08x (type=%u cbndx=%u privcfg=%u)\n",
idx, ARM_SMMU_GR0_S2CR(idx),
(u64)smmu->ioaddr + ARM_SMMU_GR0_S2CR(idx),
arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_S2CR(idx)), type, cbndx, s2cr->privcfg);
}

static int qcom_smmu_def_domain_type(struct device *dev)
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