Cache Simulator

A configurable set-associative CPU cache simulator written in C. It models a cache hierarchy and reports hit/miss behavior for a stream of memory accesses, with cache size, associativity, and block size all parameterizable at runtime.

Features

• Configurable cache size, associativity (direct-mapped through fully associative), and block size.
• Automatic derivation of set count, index/offset bit widths, and address masks from the configuration.
• LRU replacement with per-set timestamps.
• Tracks detailed statistics: read hits, write hits, read misses, write misses, evictions, and write-backs.
• Cache can be chained to a backing "main memory" level.

Repository structure

File	Purpose
csim.c / csim.h	Core simulator: cache allocation, lookup, and statistics
YOURCODEHERE.c / .h	Cache indexing/replacement logic (size, offset, and mask fields)
utils.c / utils.h	Helpers
NMM-cachesim.c, NMM.h	Driver / trace handling
Makefile	Build configuration

Building & running

make
./cachesim   # run against a memory-access trace

Built for a graduate computer-systems course.