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arch/riscv: Add CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI for fence.i#19229

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xiaoxiang781216 merged 1 commit into
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wangchdo:master
Jun 27, 2026
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arch/riscv: Add CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI for fence.i#19229
xiaoxiang781216 merged 1 commit into
apache:masterfrom
wangchdo:master

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Summary

The fence.i instruction is only available when the Zifencei extension (CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI)
is supported by the hardware.

This commit adds a macro wrapper around fence.i usages to prevent compilation errors
on toolchains or targets where the Zifencei extension is absent.

Impact

Fix compilation errors on toolchains or targets where the Zifencei extension is absent

Testing

'''
ostest passed on rv-virt:nsh

NuttShell (NSH)
nsh>
nsh>
nsh> uname -a
NuttX 0.0.0 5e1b109-dirty Jun 27 2026 22:53:48 risc-v rv-virt
nsh>
nsh> ostest
stdio_test: write fd=1
stdio_test: Standard I/O Check: printf
stdio_test: write fd=2
stdio_test: Standard I/O Check: fprintf to stderr
ostest_main: putenv(Variable1=BadValue3)
ostest_main: setenv(Variable1, GoodValue1, TRUE)
ostest_main: setenv(Variable2, BadValue1, FALSE)
ostest_main: setenv(Variable2, GoodValue2, TRUE)
ostest_main: setenv(Variable3, GoodValue3, FALSE)
ostest_main: setenv(Variable3, BadValue2, FALSE)
show_variable: Variable=Variable1 has value=GoodValue1
show_variable: Variable=Variable2 has value=GoodValue2
show_variable: Variable=Variable3 has value=GoodValue3
ostest_main: Started user_main at PID=4

user_main: Begin argument test
user_main: Started with argc=5
user_main: argv[0]="ostest"
user_main: argv[1]="Arg1"
user_main: argv[2]="Arg2"
user_main: argv[3]="Arg3"
user_main: argv[4]="Arg4"

...

End of test memory usage:
VARIABLE BEFORE AFTER
======== ======== ========
arena 1fcd580 1fcd580
ordblks 3 3
mxordblk 1fc6fe0 1fc6fe0
uordblks 4330 4330
fordblks 1fc9250 1fc9250

user_main: vfork() test
vfork_test: Child 79 ran successfully

Final memory usage:
VARIABLE BEFORE AFTER
======== ======== ========
arena 1fcd580 1fcd580
ordblks 2 3
mxordblk 1fc92a0 1fc6fe0
uordblks 42c0 4330
fordblks 1fc92c0 1fc9250
user_main: Exiting
ostest_main: Exiting with status 0
nsh>

'''

@github-actions github-actions Bot added Area: Build system Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Size: S The size of the change in this PR is small labels Jun 27, 2026
@github-actions

github-actions Bot commented Jun 27, 2026

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MemBrowse Memory Report

esp32-devkitc

  • ROM: .flash.text -8 B (-0.0%, 119,772 B / 4,194,272 B, total: 3% used)
  • irom0_0_seg: .flash.text -8 B (-0.0%, 85,052 B / 3,342,304 B, total: 3% used)

hifive1-revb

  • flash: .text +4 B (+0.0%, 80,196 B / 4,194,304 B, total: 2% used)

qemu-armv8a

  • Code: .rodata +8 B, .text.cmd_echo -16 B (-0.0%, 312,150 B)

qemu-intel64

  • Code: .text -3 B (-0.0%, 8,653,200 B)

rx65n-rsk2mb

The fence.i instruction is only available when the Zifencei extension
(CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI) is supported by the hardware.

This commit adds a macro wrapper around fence.i usages to prevent
compilation errors on toolchains or targets where the Zifencei
extension is absent.

Signed-off-by: Chengdong Wang <wangcd91@gmail.com>
@xiaoxiang781216 xiaoxiang781216 merged commit 1924a96 into apache:master Jun 27, 2026
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Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Size: S The size of the change in this PR is small

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