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feat(simai): SimAI 1.7 - SimCCL v2.30 integration, docs update, send_lat bucketing#294

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feat(simai): SimAI 1.7 - SimCCL v2.30 integration, docs update, send_lat bucketing#294
tianhao909 wants to merge 6 commits into
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@tianhao909 tianhao909 commented Jul 7, 2026

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Summary

SimAI 1.7: SimCCL v2.30 integration (NCCL-style collective flow decomposition) plus review fixes — MockNccl fully relocated to SimCCL, ns3 back to debug, EndToEnd null-guard.

Key Changes

MockNccl relocation to SimCCL

  • Removed the astra-sim/system/ MockNccl shims and in-tree mock implementations; mock now lives solely in SimCCL (SimCCL/src/mock/<version>).
  • Redirected all 23 source includes to SimCCL/mock/MockNccl*.h; updated mock source path to SimCCL/src/mock (astra-sim CMakeLists.txt, astra_ns3/build.sh, analytical symlink); added the same symlink + include root to simai_phy/CMakeLists.txt.

EndToEnd null-deref guard

  • Layer::report uses if (seprate_log && EndToEnd). end_to_end is null on non-zero ranks / when the writer isn't created (Workload.cc L53/L67/L71); the guard prevents a null dereference (segfault). Defensive fix; no behavior change with a valid writer.

ns3 back to debug (reverted from optimized)

  • scripts/build.sh symlink → ns3.36.1-AstraSimNetwork-debug; astra-sim-alibabacloud/build/astra_ns3/build.sh./ns3 configure -d debug --enable-mtp.

SimCCL v2.30 + docs

  • send_lat bucketing by (algorithm, protocol, link_type); NcclFlowModel flowTag propagation; default mock v2.30.
  • README (EN/CN/JA) 1.7 notes; docs navigation; CHANGELOG.

Dependencies (land together)

After all three merge, the SimCCL/ns-3 submodule pointers here are bumped to the merge commits.

Quick Verification (Ubuntu 24.04, GCC 13.3.0; integrated monorepo)

# analytical
./scripts/build.sh -c analytical
./bin/SimAI_analytical -w ./example/workload_analytical.txt -g 9216 -nv 360 -nic 48.5 -n_p_s 8 -g_p_s 8 -r example-

# ns3 (debug)
./scripts/build.sh -c ns3   # bin/SimAI_simulator => ns3.36.1-AstraSimNetwork-debug
AS_SEND_LAT=3 AS_NVLS_ENABLE=1 ./bin/SimAI_simulator -t 16 -w ./example/microAllReduce.txt -n ./Rail_Opti_SingleToR_8g_8gps_200Gbps_H20 -c astra-sim-alibabacloud/inputs/config/SimAI.conf

Part of SimAI 1.7 Release

Copilot AI review requested due to automatic review settings July 7, 2026 10:26
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Pull request overview

SimAI 1.7 release update centered on integrating SimCCL mock v2.30 (protocol/algorithm-aware NCCL-style flow decomposition), along with supporting build-system wiring, example workloads/configs, and expanded documentation/navigation.

Changes:

  • Integrate SimCCL mock v2.30 into ns3 + analytical builds (version selection via SIMAI_NCCL_VERSION) and propagate flow metadata (algorithm/protocol).
  • Add/refresh documentation pages (getting started, env vars, build options, docs index) plus release changelog and example workloads/configs.
  • Add Dockerfile + small infra tweaks (ns3 optimized build symlink path, expanded .gitignore, submodule URL updates).

Reviewed changes

Copilot reviewed 44 out of 191 changed files in this pull request and generated 6 comments.

Show a summary per file
File Description
scripts/build.sh Point ns3 binary symlink to optimized build output
example/workload_fth/None-None-world_size1-tp1-pp1-ep1-gbs4-mbs1-seq2048-MOE-False-GEMM-False-flash_attn-False.txt Add workload sample (FTH format)
example/workload_analytical_fth.txt Add analytical workload sample
example/microAllReduce.txt Add micro AllReduce workload sample
example/busbw.yaml Add example bus bandwidth config
docs/README.md Add docs navigation landing page
docs/getting_started/installation.md Add installation/build instructions (EN)
docs/configuration/env-variables.md Add env var reference (EN)
docs/configuration/build-options.md Add build options + CLI parameter docs (EN)
Dockerfile Add full-stack container recipe
CHANGELOG.md Add 1.5–1.7 changelog
astra-sim-alibabacloud/LICENSE Add MIT license file for vendored AstraSim tree
astra-sim-alibabacloud/inputs/config/SimAI.conf Add default ns3 simulation config file
astra-sim-alibabacloud/CMakeLists.txt Add mock version selection + glob SimCCL mock sources
astra-sim-alibabacloud/build/simai_phy/CMakeLists.txt Add physical build CMake entry
astra-sim-alibabacloud/build/simai_analytical/CMakeLists.txt Add analytical mock-version selection + symlink include strategy
astra-sim-alibabacloud/build/astra_ns3/CMakeLists.txt Add ns3 build CMake entry
astra-sim-alibabacloud/build/astra_ns3/build.sh Copy versioned mock into ns3 app tree; switch to optimized ns3 build
astra-sim-alibabacloud/astra-sim/workload/Workload.hh Add/restore workload interface definition
astra-sim-alibabacloud/astra-sim/workload/Workload.cc Guard dimension utilization finalize on null writer
astra-sim-alibabacloud/astra-sim/workload/CSVWriter.hh Add CSV writer helper
astra-sim-alibabacloud/astra-sim/system/UsageTracker.hh Add usage tracking interface
astra-sim-alibabacloud/astra-sim/system/UsageTracker.cc Add usage tracking implementation
astra-sim-alibabacloud/astra-sim/system/Usage.hh Add usage record type
astra-sim-alibabacloud/astra-sim/system/Usage.cc Add usage record implementation
astra-sim-alibabacloud/astra-sim/system/topology/Torus3D.hh Add Torus3D topology
astra-sim-alibabacloud/astra-sim/system/topology/Torus3D.cc Add Torus3D topology implementation
astra-sim-alibabacloud/astra-sim/system/topology/RingTopology.hh Add ring topology definition
astra-sim-alibabacloud/astra-sim/system/topology/Node.hh Add tree node definition
astra-sim-alibabacloud/astra-sim/system/topology/Node.cc Add tree node implementation
astra-sim-alibabacloud/astra-sim/system/topology/LogicalTopology.hh Add logical topology base interface
astra-sim-alibabacloud/astra-sim/system/topology/LogicalTopology.cc Add logical topology helpers
astra-sim-alibabacloud/astra-sim/system/topology/LocalRingNodeA2AGlobalDBT.hh Add composite topology type
astra-sim-alibabacloud/astra-sim/system/topology/LocalRingNodeA2AGlobalDBT.cc Add composite topology implementation
astra-sim-alibabacloud/astra-sim/system/topology/LocalRingGlobalBinaryTree.hh Add composite topology type
astra-sim-alibabacloud/astra-sim/system/topology/LocalRingGlobalBinaryTree.cc Add composite topology implementation
astra-sim-alibabacloud/astra-sim/system/topology/GeneralComplexTopology.hh Add general complex topology
astra-sim-alibabacloud/astra-sim/system/topology/GeneralComplexTopology.cc Adjust flow-model topology condition for NcclFlowModel
astra-sim-alibabacloud/astra-sim/system/topology/DoubleBinaryTreeTopology.hh Add DBT topology definition
astra-sim-alibabacloud/astra-sim/system/topology/DoubleBinaryTreeTopology.cc Add DBT topology implementation
astra-sim-alibabacloud/astra-sim/system/topology/ComputeNode.hh Add compute-node stub base
astra-sim-alibabacloud/astra-sim/system/topology/ComplexLogicalTopology.hh Add complex topology base
astra-sim-alibabacloud/astra-sim/system/topology/BinaryTree.hh Add binary tree topology definition
astra-sim-alibabacloud/astra-sim/system/topology/BinaryTree.cc Add binary tree topology implementation
astra-sim-alibabacloud/astra-sim/system/topology/BasicLogicalTopology.hh Add basic topology base
astra-sim-alibabacloud/astra-sim/system/Sys.cc Switch to NcclFlowModel; add analytical ratio CSV loading; add PAT handling
astra-sim-alibabacloud/astra-sim/system/StreamStat.hh Add stream stat aggregation
astra-sim-alibabacloud/astra-sim/system/StreamBaseline.hh Add baseline stream type
astra-sim-alibabacloud/astra-sim/system/StreamBaseline.cc Add baseline stream implementation
astra-sim-alibabacloud/astra-sim/system/StatData.hh Add stat call-data type
astra-sim-alibabacloud/astra-sim/system/SimSendCaller.hh Add deferred send wrapper
astra-sim-alibabacloud/astra-sim/system/SimSendCaller.cc Add deferred send wrapper implementation
astra-sim-alibabacloud/astra-sim/system/SimRecvCaller.hh Add deferred recv wrapper
astra-sim-alibabacloud/astra-sim/system/SimRecvCaller.cc Add deferred recv wrapper implementation
astra-sim-alibabacloud/astra-sim/system/SimAiPhyCommon.hh Add physical-network shared structs/constants
astra-sim-alibabacloud/astra-sim/system/SimAiFlowModelRdma.hh Add RDMA flow modeling declarations
astra-sim-alibabacloud/astra-sim/system/SendPacketEventHandlerData.hh Add send packet handler data structure
astra-sim-alibabacloud/astra-sim/system/SendPacketEventHandlerData.cc Add send packet handler data implementation
astra-sim-alibabacloud/astra-sim/system/scheduling/OfflineGreedy.hh Add offline greedy scheduler interface
astra-sim-alibabacloud/astra-sim/system/RendezvousSendData.hh Add rendezvous send call-data
astra-sim-alibabacloud/astra-sim/system/RendezvousSendData.cc Add rendezvous send call-data implementation
astra-sim-alibabacloud/astra-sim/system/RendezvousRecvData.hh Add rendezvous recv call-data
astra-sim-alibabacloud/astra-sim/system/RendezvousRecvData.cc Add rendezvous recv call-data implementation
astra-sim-alibabacloud/astra-sim/system/RecvPacketEventHadndlerData.hh Add recv packet handler data
astra-sim-alibabacloud/astra-sim/system/RecvPacketEventHadndlerData.cc Add recv packet handler data implementation
astra-sim-alibabacloud/astra-sim/system/QueueLevels.hh Add queue-level allocator interface
astra-sim-alibabacloud/astra-sim/system/QueueLevels.cc Add queue-level allocator implementation
astra-sim-alibabacloud/astra-sim/system/QueueLevelHandler.hh Add queue-level handler interface
astra-sim-alibabacloud/astra-sim/system/QueueLevelHandler.cc Add queue-level handler implementation
astra-sim-alibabacloud/astra-sim/system/PhyMultiThread.hh Add physical multi-thread interfaces/locks
astra-sim-alibabacloud/astra-sim/system/PacketBundle.hh Add packet bundle wrapper type
astra-sim-alibabacloud/astra-sim/system/PacketBundle.cc Add packet bundle implementation
astra-sim-alibabacloud/astra-sim/system/NetworkStat.hh Add network stat aggregation
astra-sim-alibabacloud/astra-sim/system/MyPacket.hh Add packet representation
astra-sim-alibabacloud/astra-sim/system/MyPacket.cc Add packet implementation
astra-sim-alibabacloud/astra-sim/system/MockNcclQps.h Forwarding header to SimCCL mock location
astra-sim-alibabacloud/astra-sim/system/MockNcclLog.h Forwarding header to SimCCL mock location
astra-sim-alibabacloud/astra-sim/system/MockNcclLog.cc Add MockNcclLog static definitions
astra-sim-alibabacloud/astra-sim/system/MockNcclChannel.h Forwarding header to SimCCL mock location
astra-sim-alibabacloud/astra-sim/system/MockNcclChannel.cc Add MockNcclComm wrapper implementation
astra-sim-alibabacloud/astra-sim/system/memory/SimpleMemory.hh Add simple memory model interface
astra-sim-alibabacloud/astra-sim/system/memory/SimpleMemory.cc Add simple memory model implementation
astra-sim-alibabacloud/astra-sim/system/MemMovRequest.hh Add memory movement request type
astra-sim-alibabacloud/astra-sim/system/MemMovRequest.cc Add memory movement request implementation
astra-sim-alibabacloud/astra-sim/system/MemBus.hh Add memory bus abstraction
astra-sim-alibabacloud/astra-sim/system/MemBus.cc Add memory bus implementation
astra-sim-alibabacloud/astra-sim/system/LogGP.hh Add LogGP model interface
astra-sim-alibabacloud/astra-sim/system/IntData.hh Add integer call-data wrapper
astra-sim-alibabacloud/astra-sim/system/DMA_Request.hh Add DMA request type
astra-sim-alibabacloud/astra-sim/system/DMA_Request.cc Add DMA request implementation
astra-sim-alibabacloud/astra-sim/system/DataSet.hh Add dataset aggregation type
astra-sim-alibabacloud/astra-sim/system/DataSet.cc Add dataset aggregation implementation
astra-sim-alibabacloud/astra-sim/system/Common.hh Add H20 GPU type; add Broadcast; remove NcclTreeFlowModel enum
astra-sim-alibabacloud/astra-sim/system/CollectivePhase.hh Add collective phase wrapper
astra-sim-alibabacloud/astra-sim/system/CollectivePhase.cc Add collective phase implementation
astra-sim-alibabacloud/astra-sim/system/collective/Ring.hh Add ring algorithm interface
astra-sim-alibabacloud/astra-sim/system/collective/NcclTreeFlowModel.hh Keep legacy tree flow model header (present in tree)
astra-sim-alibabacloud/astra-sim/system/collective/NcclFlowModel.hh Add unified flow model with algo/proto tagging
astra-sim-alibabacloud/astra-sim/system/collective/HalvingDoubling.hh Add halving-doubling algorithm interface
astra-sim-alibabacloud/astra-sim/system/collective/DoubleBinaryTreeAllReduce.hh Add DBT allreduce algorithm interface
astra-sim-alibabacloud/astra-sim/system/collective/AllToAll.hh Add all-to-all algorithm interface
astra-sim-alibabacloud/astra-sim/system/collective/AllToAll.cc Add all-to-all algorithm implementation
astra-sim-alibabacloud/astra-sim/system/collective/Algorithm.hh Add algorithm base interface
astra-sim-alibabacloud/astra-sim/system/collective/Algorithm.cc Add algorithm base implementation
astra-sim-alibabacloud/astra-sim/system/CallData.hh Add call-data base type
astra-sim-alibabacloud/astra-sim/system/Callable.hh Add callable base type
astra-sim-alibabacloud/astra-sim/system/BootStrapnet.hh Add MPI bootstrap declarations
astra-sim-alibabacloud/astra-sim/system/BootStrapnet.cc Add MPI bootstrap implementation
astra-sim-alibabacloud/astra-sim/system/BasicEventHandlerData.hh Add basic event handler data type
astra-sim-alibabacloud/astra-sim/system/BasicEventHandlerData.cc Add basic event handler data implementation
astra-sim-alibabacloud/astra-sim/system/BaseStream.hh Add base stream interface
astra-sim-alibabacloud/astra-sim/system/BaseStream.cc Add base stream implementation
astra-sim-alibabacloud/astra-sim/system/AstraSimDataAPI.hh Add stats API data structures
astra-sim-alibabacloud/astra-sim/system/AstraParamParse.cc Add static definitions for argument parser
astra-sim-alibabacloud/astra-sim/system/AstraNetworkAPI.hh Extend ncclFlowTag with algorithm/protocol/gpus_per_node
astra-sim-alibabacloud/astra-sim/system/AstraMemoryAPI.hh Add memory API interface
astra-sim-alibabacloud/astra-sim/system/AstraComputeAPI.hh Add compute API interface
astra-sim-alibabacloud/astra-sim/network_frontend/phynet/SimAiPhyNetwork.h Add physical network frontend API
astra-sim-alibabacloud/astra-sim/network_frontend/phynet/SimAiPhyNetwork.cc Add physical network frontend implementation
astra-sim-alibabacloud/astra-sim/network_frontend/phynet/SimAiEntry.h Add physical entrypoint declarations
astra-sim-alibabacloud/astra-sim/network_frontend/phynet/SimAiEntry.cc Add physical callback wiring + RDMA send wrapper
astra-sim-alibabacloud/astra-sim/network_frontend/phynet/PhySimAi.h Add physical scheduler declarations
astra-sim-alibabacloud/astra-sim/network_frontend/phynet/PhySimAi.cc Add physical scheduler implementation
astra-sim-alibabacloud/astra-sim/network_frontend/phynet/CMakeLists.txt Add phynet build rules
astra-sim-alibabacloud/astra-sim/network_frontend/ns3/AstraSimNetwork.h Add ns3 network header stub
astra-sim-alibabacloud/astra-sim/network_frontend/analytical/CMakeLists.txt Add analytical build rules
astra-sim-alibabacloud/astra-sim/network_frontend/analytical/AnaSim.h Add analytical scheduler declarations
astra-sim-alibabacloud/astra-sim/network_frontend/analytical/AnaSim.cc Add analytical scheduler implementation
astra-sim-alibabacloud/astra-sim/network_frontend/analytical/AnalyticalNetwork.h Add analytical network frontend API
astra-sim-alibabacloud/astra-sim/network_frontend/analytical/AnalyticalNetwork.cc Add analytical network frontend implementation
astra-sim-alibabacloud/astra-sim/network_frontend/analytical/AnalyticalAstra.cc Add analytical executable entrypoint
.gitmodules Switch submodule URLs (currently to SSH)
.gitignore Ignore build artifacts, results, and editor temp files

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#include "Common.hh"
#include "RendezvousRecvData.hh"
#include "RendezvousSendData.hh"
#include "calbusbw.h"
Comment thread Dockerfile Outdated
Comment on lines +11 to +13
RUN pip config set global.index-url http://mirrors.aliyun.com/pypi/simple
RUN pip config set install.trusted-host mirrors.aliyun.com
ENV UV_DEFAULT_INDEX="https://mirrors.aliyun.com/pypi/simple"
Comment thread Dockerfile Outdated
Comment on lines +29 to +31
RUN mv ./workload_generator /usr/local/lib/python3.12/dist-packages &&\
mv ./utils /usr/local/lib/python3.12/dist-packages &&\
mv ./log_analyzer /usr/local/lib/python3.12/dist-packages
Comment thread .gitmodules Outdated
[submodule "SimCCL"]
path = SimCCL
url = https://github.com/aliyun/SimCCL
url = git@github.com:aliyun/SimCCL
Comment thread .gitmodules Outdated
[submodule "aicb"]
path = aicb
url = https://github.com/aliyun/aicb
url = git@github.com:aliyun/aicb.git
Comment thread .gitmodules Outdated
[submodule "ns-3-alibabacloud"]
path = ns-3-alibabacloud
url = https://github.com/aliyun/ns-3-alibabacloud
url = git@github.com:aliyun/ns-3-alibabacloud
@tianhao909
tianhao909 force-pushed the simai1_7_pr_260707_1249 branch from 6e5e727 to d83189a Compare July 7, 2026 10:50
…lat bucketing

[EN]
- Integrate SimCCL v2.30 mock: update astra-sim forwarding headers, entry.h send_lat bucketing, NcclFlowModel, Sys.cc flowTag
- Change default mock version to v2.30 (build.sh, CMakeLists.txt)
- Add SimCCL mock version selection for analytical build
- Update README (EN/CN/JA): 1.7 release notes, Use SimCCL section, fix links
- Add docs/README.md navigation, docs/CN/Tutorial.md translation
- Add CHANGELOG.md (v1.5/v1.6/v1.7)
- Update docs/getting_started with v2.30 default note and SimCCL standalone section
- Add H20 topology configs (128gpu/64gpu/16gpu)
- Fix scripts/build.sh symlink target

[ZH]
- 集成 SimCCL v2.30 mock:更新 astra-sim 转发头文件、entry.h send_lat 分桶、NcclFlowModel、Sys.cc flowTag
- 默认 mock 版本改为 v2.30(build.sh、CMakeLists.txt)
- 为 analytical 构建添加 SimCCL mock 版本选择
- 更新 README(中/英/日):1.7 发布说明、Use SimCCL 段落、修复链接
- 添加 docs/README.md 导航、docs/CN/Tutorial.md 中文翻译
- 添加 CHANGELOG.md(v1.5/v1.6/v1.7)
- 更新 docs/getting_started(v2.30 默认说明 + SimCCL standalone 章节)
- 添加 H20 拓扑配置(128gpu/64gpu/16gpu)
- 修复 scripts/build.sh symlink 目标
@tianhao909
tianhao909 force-pushed the simai1_7_pr_260707_1249 branch from d83189a to 632e146 Compare July 7, 2026 12:00
#endif // ASTRA_SIM_MOCKNCCL_MOCKNCCL_H
// Forwarding header: MockNccl was relocated into SimCCL/mock/ (Task 3, 2026-06-02).
// Kept here so existing includes "astra-sim/system/MockNccl.h" keep working.
#include "SimCCL/mock/MockNccl.h"

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mocknccl.h删掉

layerData.avg_network_message_dealy.push_back(std::make_pair(i, ml / FREQ));
}
if (seprate_log)
if (seprate_log && EndToEnd)

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EndToEnd的作用?

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定义在 343行, 之前版本就有的代码

CSVWriter* EndToEnd,
Image

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看下判断EndToEnd需要存在的作用,是否为了修复某些bug,例如文件不存在导致的报错

int total_rows,
int stat_row,
CSVWriter* detailed,
CSVWriter* EndToEnd,

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EndToEnd 定义在这边 , 已有的代码 @MXtremist

…compat shims

[EN]
- Untrack 3 generated topology files (Rail_Opti_SingleToR_16g/64gpu/128gpu_8gps_200Gbps_H20);
  kept locally via .gitignore. They are produced by
  astra-sim-alibabacloud/inputs/topo/gen_Topo_Template.py (see quickstart step 2).
- .gitignore: ignore astra-sim-alibabacloud/inputs/topo/Rail_Opti_SingleToR_* and
  repo-root /Rail_Opti_SingleToR_* (generation output).
- Keep the 5 MockNccl forwarding headers (astra-sim/system/MockNccl{,Channel,Group,Log,Qps}.h)
  as backward-compatible shims to SimCCL/mock/*; ~25 sources still include the
  astra-sim/system/ paths, so the shims are intentional (not dead code).

[ZH]
- 取消跟踪 3 个生成的拓扑文件(Rail_Opti_SingleToR_16g/64gpu/128gpu_8gps_200Gbps_H20),
  通过 .gitignore 本地保留;它们由
  astra-sim-alibabacloud/inputs/topo/gen_Topo_Template.py 生成(见 quickstart 第 2 步)。
- .gitignore:忽略 astra-sim-alibabacloud/inputs/topo/Rail_Opti_SingleToR_* 与
  仓根 /Rail_Opti_SingleToR_*(生成产物)。
- 保留 5 个 MockNccl 转发头(astra-sim/system/MockNccl{,Channel,Group,Log,Qps}.h)
  作为到 SimCCL/mock/* 的向后兼容 shim;约 25 个源文件仍通过 astra-sim/system/
  路径 include,故 shim 为有意保留(非无用代码)。
@tianhao909

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Review update (round 2)

Changes

  • Untrack 3 generated topology files (Rail_Opti_SingleToR_{16g,64gpu,128gpu}_8gps_200Gbps_H20) via git rm --cached; kept locally and ignored (.gitignore now covers astra-sim-alibabacloud/inputs/topo/Rail_Opti_SingleToR_* and repo-root /Rail_Opti_SingleToR_*). They are produced by inputs/topo/gen_Topo_Template.py (quickstart step 2).
  • Keep the 5 astra-sim/system/MockNccl*.h forwarding headers: they are intentional backward-compat shims to SimCCL/mock/* (~25 sources still include the astra-sim/system/ paths), so they are not dead code and are retained.

Tests

  • Full simulator end-to-end: generated the 16g topology then ran ./bin/SimAI_simulator -t 8 -w ./example/microAllReduce_16g.txt -n ./Rail_Opti_SingleToR_16g_8gps_200Gbps_H20 -c .../SimAI.conf -> exit 0, all 16 nodes reached sim_finish (146800640 B each). No regression.

Submodule note (ordering)

  • SimCCL/aicb/ns-3-alibabacloud gitlinks point to aliyun upstream master (403610a / 23eec3c / 7e3cb5b), matching PR#4 and ns-3 PR#22 base. After SimCCL#4 and ns-3#22 merge into aliyun master, the submodule pointers here should be bumped to the new master HEADs.

Review 更新(第 2 轮)

改动

  • 通过 git rm --cached 取消跟踪 3 个生成的拓扑文件(Rail_Opti_SingleToR_{16g,64gpu,128gpu}_8gps_200Gbps_H20);本地保留并忽略(.gitignore 覆盖 astra-sim-alibabacloud/inputs/topo/Rail_Opti_SingleToR_* 与仓根 /Rail_Opti_SingleToR_*)。它们由 inputs/topo/gen_Topo_Template.py 生成(quickstart 第 2 步)。
  • 保留 5 个 astra-sim/system/MockNccl*.h 转发头:它们是到 SimCCL/mock/* 的有意向后兼容 shim(约 25 个源文件仍通过 astra-sim/system/ 路径 include),并非无用代码,予以保留。

测试

  • 完整仿真端到端:生成 16g 拓扑后运行 ./bin/SimAI_simulator -t 8 -w ./example/microAllReduce_16g.txt -n ./Rail_Opti_SingleToR_16g_8gps_200Gbps_H20 -c .../SimAI.conf -> exit 0,16 个节点全部 sim_finish(各 146800640 字节),无回归。

Submodule 说明(顺序依赖)

  • SimCCL/aicb/ns-3-alibabacloud 的 gitlink 指向 aliyun 上游 master403610a / 23eec3c / 7e3cb5b),与 PR#4、ns-3 PR#22 的 base 一致。待 SimCCL#4 与 ns-3#22 合入 aliyun master 后,此处 submodule 指针应 bump 到新的 master HEAD。

[EN]
- Remove astra-sim/system/MockNccl.h forwarding shim: verified 0 references via the "astra-sim/system/MockNccl.h" include path (repo-wide grep); full ns3 build + microAllReduce e2e pass without it (addresses PR aliyun#294 request to delete mocknccl.h)
- Dockerfile: use HTTPS pip index (drop http + trusted-host) to avoid MITM; compute site-packages path dynamically instead of hardcoding python3.12/dist-packages

[ZH]
- 删除 astra-sim/system/MockNccl.h 转发 shim:经全仓 grep 确认无任何经该路径的 include(0 引用);删除后全量 ns3 构建 + microAllReduce 端到端仿真均通过(回应 PR aliyun#294 删除 mocknccl.h 的要求)
- Dockerfile:pip 源改用 HTTPS(去掉 http 与 trusted-host)避免 MITM;site-packages 路径动态计算,不再硬编码 python3.12/dist-packages
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Review 修复 + 5.1 分析 + 测试结果 / Review fixes + shim analysis + tests

Commit: 9e83aba (on tianhao909:simai1_7_pr_260707_1249)

5.1 Mock shim 可行性分析(先分析后删)/ Mock shim analysis

astra-sim-alibabacloud/astra-sim/system/ 下 5 个转发 shim 做全仓精确检索(astra-sim/system/MockNccl*.h include 路径):

Shim astra-sim/system/ 路径的引用数 处理
MockNccl.h 0(仅自身注释) 已删除
MockNcclLog.h 13(Sys.cc/Workload.cc/Layer.cc/MemBus.cc/PacketBundle.cc/entry.h/…) 保留
MockNcclQps.h 3(entry.h/NcclFlowModel.hh/SimAiEntry.h) 保留
MockNcclGroup.h 2(Sys.hh/Layer.hh) 保留
MockNcclChannel.h 1(Sys.hh) 保留

结论MockNccl.h 为零引用死代码,已删除(对应 reviewer “mocknccl.h 删掉”)。其余 4 个被 20+ 处核心头/源引用,是跨构建模式(ns3 / analytical / phynet)的稳定转发头,删除需重指且高风险、收益低,故保留。删除 MockNccl.h全量 ns3 构建 + 端到端仿真均通过(见下)。/ MockNccl.h was dead (0 refs) and removed; the other 4 are load-bearing forwarding headers referenced by 20+ core sites and are kept.

对其余 review 的回复 / Replies

  • Sys.cc #include "calbusbw.h" 无条件 include (Copilot:“header not present, breaks all builds”): 经核实,calbusbw.h 确实存在astra-sim-alibabacloud/astra-sim/system/calbusbw.h(git 跟踪,与 Sys.cc 同目录),且 cal_busbw 等符号在 Sys.cc 中并未使用。ns3 与 analytical 两个 target 均能成功编译(本次 ns3 全量构建 0 error)。故该 review 的前提(头文件缺失)不成立,保持现状不改,避免对可用代码做无谓改动。/ calbusbw.h is present and both ns3 & analytical compile; the premise (missing header) does not hold, so no change.
  • .gitmodules SSH URL (Copilot): 当前已是 HTTPS(https://github.com/aliyun/...),该项已解决。/ Already HTTPS.
  • Layer.cc EndToEnd (MXtremist): 为旧版本已有代码(CSVWriter* EndToEndastra-sim-alibabacloud/astra-sim/workload/Layer.cc),非本 PR 引入,无需改动。/ Pre-existing code, no change.
  • Dockerfile (Copilot): pip 源 http://https:// 且移除 trusted-host(避免 MITM);python3.12/dist-packages 硬编码改为 python3 -c 'import site; print(site.getsitepackages()[0])' 动态计算。✅

静态测试(全量 ns3 构建)/ Static test (full ns3 build)

bash scripts/build.sh -c ns3
  -> [1077/1078] Linking CXX executable ns3.36.1-AstraSimNetwork-optimized
  -> 0 compile errors;bin/SimAI_simulator 更新

compiler: g++ 13.3.0 / cmake 3.31.6。删除 MockNccl.h 后无任何编译错误。

动态测试(端到端仿真)/ Dynamic test (e2e simulation)

python3 ./astra-sim-alibabacloud/inputs/topo/gen_Topo_Template.py --ro -g 8 -gt H20 -bw 200Gbps -nvbw 2400Gbps
  -> Rail_Opti_SingleToR_8g_8gps_200Gbps_H20
./bin/SimAI_simulator -t 8 -w ./example/microAllReduce.txt \
    -n ./Rail_Opti_SingleToR_8g_8gps_200Gbps_H20 \
    -c ./astra-sim-alibabacloud/inputs/config/SimAI.conf
  -> RUN_EXIT=0;node 0-7 各收发 146800640 bytes
  -> 产物: ncclFlowModel_EndToEnd.csv / ncclFlowModel_detailed_flows.csv / *_dimension_utilization_0.csv

依赖声明 / Dependencies

本 PR 依赖 aliyun/SimCCL#4(SimCCL v2.30 mock)与 aliyun/ns-3-alibabacloud#22(CMake glob),需三者一起合并。submodule 指针当前指向 aliyun upstream base(SimCCL 403610a / aicb 23eec3c / ns3 7e3cb5b),待 #4/#22 合并后再更新为 merge commit;端到端测试在整合好的开发仓内嵌目录进行。合并前单独 clone 本 PR + submodule update 无法直接复现(多仓联动 PR 的正常现象)。

注:本条为测试记录,不进入 PR 文件。/ Note: this is a test record, not committed into the PR.

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三仓统一端到端集成测试 / Unified 3-repo end-to-end test

在整合好的开发仓(SimCCL v2.30 + ns3 CMake glob + 本 PR astra-sim 改动)上,三仓改动合并后的完整验证。

构建矩阵 / Build matrix

Mode Command Result
ns3 (full) bash scripts/build.sh -c ns3 [1077/1078] Linking ns3.36.1-AstraSimNetwork-optimized, 0 error
analytical bash scripts/build.sh -c analytical Built target SimAI_analytical, 0 error
SimCCL standalone bash build.sh v2.30 / v2.20 ✅ 326560 B / 304528 B

compiler: g++ 13.3.0 / cmake 3.31.6。删除 MockNccl.h shim 后三种模式均无编译错误。

ns3 端到端 + send_lat A/B(与 docs/getting_started/quickstart.md 预期值逐一对择)

8 GPU / H20 / Rail_Opti_SingleToR_8g_8gps_200Gbps_H20 / microAllReduce.txt

Condition total time (实测) 文档预期 匹配
Baseline (send_lat_table) 389404.030 389,404
AS_SEND_LAT=6000 169604.030 169,604
AS_SEND_LAT=6 1772.030 1,772

另:16 GPU / 2 节点跨节点(microAllReduce_16g.txt + Rail_Opti_SingleToR_16g_8gps_200Gbps_H20)RUN_EXIT=0,16 节点全部收发完成。

analytical 运行 / analytical run

./bin/SimAI_analytical -w ./example/workload_analytical.txt -g 9216 -nv 360 -nic 48.5 -n_p_s 8 -g_p_s 8 -r example-
  -> exit 0, "SimAI-Analytical finished." (Collective implementation: NcclFlowModel)

坦诚标注 / Caveats

  • README 中 ./bin/SimAI_analytical ... -busbw example/busbw.yaml-busbw 在当前二进制参数解析器(AstraParamParse.hh)中并非有效 flag(解析器仅有 -nic/-n_p_s 等),属既有文档/二进制不一致,与本次三个 PR 无关;用 README 另一条有效参数命令可正常运行。
  • phy 模式需多机 mpirun,本单机环境不具备,未测。

注:本条为测试记录,不进入 PR 文件。/ Note: test record, not committed into the PR.

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回退一下,默认使用optimized可能导致bug

Comment thread astra-sim-alibabacloud/build/astra_ns3/build.sh
…back to debug

[EN]
- Remove 4 forwarding shims and 3 in-tree mock impls under astra-sim/system/
  (MockNcclChannel/Group/Log.{cc,h}, MockNcclQps.h); mock now lives solely in
  SimCCL (SimCCL/src/mock/<version>)
- Redirect all 23 remaining source includes from "astra-sim/system/MockNccl*.h"
  (and bare "MockNcclLog.h") to "SimCCL/mock/MockNccl*.h" (version-agnostic;
  resolved via the per-mode SimCCL/mock symlink or flat copy)
- Point mock source path to SimCCL/src/mock: astra-sim-alibabacloud/CMakeLists.txt
  glob, build/astra_ns3/build.sh MOCK_SRC, build/simai_analytical/CMakeLists.txt
  symlink
- Add the same SimCCL/mock symlink + include root to build/simai_phy/CMakeLists.txt
  so phy resolves SimCCL/mock consistently
- ns3 back to debug: scripts/build.sh symlink dir (-debug) and
  build/astra_ns3/build.sh `./ns3 configure -d debug --enable-mtp`
- Mock sources are provided by the SimCCL submodule (SimCCL/src/mock) once it is
  bumped to the merged SimCCL (the three PRs merge together). Validated
  end-to-end in the integrated SimAI monorepo: analytical + ns3 debug build +
  8-GPU AllReduce simulation. NcclTreeFlowModel retained with updated include
  path (its removal is a separate refactor, out of this PR's scope).

[ZH]
- 删除 astra-sim/system/ 下 4 个转发 shim 与 3 个内置 mock 实现
  (MockNcclChannel/Group/Log.{cc,h}、MockNcclQps.h);mock 现仅存于 SimCCL
  (SimCCL/src/mock/<版本>)
- 将全部 23 处源码 include 从 "astra-sim/system/MockNccl*.h"(及裸 "MockNcclLog.h")
  改为 "SimCCL/mock/MockNccl*.h"(版本无关,经各模式 SimCCL/mock 软链或平铺拷贝解析)
- mock 源路径指向 SimCCL/src/mock:astra-sim-alibabacloud/CMakeLists.txt 的 glob、
  build/astra_ns3/build.sh 的 MOCK_SRC、build/simai_analytical/CMakeLists.txt 的软链
- 为 build/simai_phy/CMakeLists.txt 补齐相同的 SimCCL/mock 软链 + include 根,
  使 phy 一致解析
- ns3 回退 debug:scripts/build.sh 软链目录(-debug)与
  build/astra_ns3/build.sh 的 `./ns3 configure -d debug --enable-mtp`
- mock 源由 SimCCL 子模块(SimCCL/src/mock)在其 bump 到合并后的 SimCCL 时提供
  (三仓一起合并)。已在 SimAI 单体仓端到端验证:analytical + ns3 debug 构建 +
  8-GPU AllReduce 仿真。NcclTreeFlowModel 保留并更新 include 路径(其删除属另一
  重构,不在本 PR 范围)。
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Update addressing review (2026-07)

system/ MockNccl.h removed + includes redirected*

  • Deleted the 4 forwarding shims and the 3 in-tree mock implementations under astra-sim/system/ (MockNcclChannel/Group/Log.{cc,h}, MockNcclQps.h). Mock now lives solely in SimCCL (SimCCL/src/mock/<version>, see SimCCL#4).
  • Redirected all 23 remaining source includes from astra-sim/system/MockNccl*.h (and bare MockNcclLog.h) to SimCCL/mock/MockNccl*.h (version-agnostic; resolved via the per-mode SimCCL/mock symlink [analytical/phy] or flat copy [ns3]).
  • Updated mock source path to SimCCL/src/mock in astra-sim-alibabacloud/CMakeLists.txt, build/astra_ns3/build.sh, and the analytical symlink; added the same symlink + include root to build/simai_phy/CMakeLists.txt.

Why the EndToEnd guard exists (re: discussion_r3548594205 / discussion_r3556075875) — it is a null-deref fix

  • In Workload.cc, end_to_end defaults to nullptr (L53) and is created only when generator->id == 0 && seprate_log (L67 → L71 new CSVWriter(...)). report() is called for every layer with (end_to_end, seprate_log).
  • So whenever seprate_log==true but the writer was not created (non-zero rank, PHY_MTP multi-rank, or writer disabled), the old if (seprate_log) in Layer::report would dereference a null EndToEnd (write_line/write_res, and EndToEnd->path for chart.html) → segfault. if (seprate_log && EndToEnd) short-circuits and removes the null dereference. It is a defensive null-guard, not a behavior change (with a valid writer the logic is identical).

ns3 back to debug (re: discussion_r3556089090 / discussion_r3556092216)

  • scripts/build.sh: symlink target ns3.36.1-AstraSimNetwork-debug (was -optimized).
  • astra-sim-alibabacloud/build/astra_ns3/build.sh: ./ns3 configure -d debug --enable-mtp (was -d optimized ... -DCMAKE_CXX_FLAGS="-g -O2"). Verified bin/SimAI_simulator resolves to the -debug binary.

Static/dynamic test (integrated SimAI monorepo, Ubuntu 24.04, GCC 13.3.0):

  • analytical build ✅; ns3 debug build ✅ (bin/SimAI_simulator → ns3.36.1-AstraSimNetwork-debug).
  • ns3 8-GPU AllReduce simulation ✅ (all 8 nodes sent/received 146800640 bytes; produced ncclFlowModel_EndToEnd.csv).
  • phy: could not be compiled in this environment (broken MPI wrapper — missing OpenMPI/HPC-X mpicxx-wrapper-data.txt); unrelated to these changes.
  • Note: these three PRs are intended to land together; #294 builds standalone once SimCCL#4 is merged and the submodule is bumped, so end-to-end validation was performed in the integrated monorepo where all three components sit side by side.

…wModel

[EN]
- Delete NcclTreeFlowModel.cc/.hh (superseded by NcclFlowModel; Sys.cc only
  instantiates NcclFlowModel, zero remaining references, dev builds clean)
- Add missing docs/CN/configuration/{build-options,env-variables,send-lat-analysis}.md
- Add missing docs/CN/getting_started/{installation,quickstart}.md to mirror EN docs

[ZH]
- 删除已废弃的 NcclTreeFlowModel.cc/.hh(已被 NcclFlowModel 取代;Sys.cc 仅实例化
  NcclFlowModel,无其它引用,dev 可干净编译)
- 补齐缺失的 docs/CN/configuration/{build-options,env-variables,send-lat-analysis}.md
- 补齐缺失的 docs/CN/getting_started/{installation,quickstart}.md,与英文文档对齐
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Test Report / 测试报告 (SimAI 1.7)

Environment: Ubuntu 24.04, g++ 13.3.0, x86_64. Tested on the integrated tree (this PR + SimCCL#4 + ns-3-alibabacloud#22).
环境:Ubuntu 24.04,g++ 13.3.0,x86_64。在三 PR 合并后的集成代码树上测试。

1. Static build / 静态构建

Target Command Result
ns3 simulator ./scripts/build.sh -c ns3 PASS — bin/SimAI_simulator linked (0 errors; only pre-existing -Wformat/-Wwrite-strings warnings)
analytical ./scripts/build.sh -c analytical PASS — bin/SimAI_analytical linked (0 errors)

2. Dynamic run — ns3 end-to-end (8 GPU, H20, example/microAllReduce.txt) / 动态运行

Topology: gen_Topo_Template.py --ro -g 8 -gt H20 -bw 200Gbps -nvbw 2400Gbps. Results reproduce the documented values in docs/getting_started/quickstart.md exactly.

Case Total time (ns) Doc value Match
Baseline (send_lat_table) 389,404 389,404 YES
AS_SEND_LAT=6 1,772 1,772 YES
AS_SEND_LAT=6000 169,604 169,604 YES
AS_SEND_LAT=7200 203,204 203,204 YES

Cross-node 16 GPU (2 nodes, all_gpus: 16): simulation completed exit 0, ranks 0-15 all active (146,800,640 bytes sent/received per node). Confirms the send_lat bucketing path (algorithm/protocol/gpus_per_node carried to flowTag) works end-to-end.
16 GPU 跨节点:仿真 exit 0,rank 0-15 全部参与,验证 send_lat 分桶路径端到端可用。

Output files generated as documented: ncclFlowModel_EndToEnd.csv, ncclFlowModel_detailed_N.csv, ncclFlowModel_detailed_flows.csv, *_dimension_utilization_*.csv.

3. Notes on this PR's changes / 本次改动说明

  • Removed deprecated NcclTreeFlowModel.cc/.hh: NcclFlowModel is a strict superset (rename + algorithm/protocol/gpus_per_node carried to flowTag). Sys.cc only instantiates NcclFlowModel; zero remaining references to NcclTreeFlowModel. Tests above pass without it.
  • Added missing docs/CN/configuration/* and docs/CN/getting_started/* so Chinese docs mirror the English set.
  • 删除废弃的 NcclTreeFlowModel.*NcclFlowModel 为其严格超集;仅 Sys.cc 实例化,无其它引用)。
  • 补齐缺失的中文文档 docs/CN/configuration/*docs/CN/getting_started/*,与英文对齐。

… unsupported -busbw

[EN]
- Promote the automatic bus-bandwidth command (-nv/-nic/-n_p_s) to the primary runnable
  analytical example across README (EN/CN/JA), build-options, and Tutorial (EN/CN)
- Retain the -busbw example/busbw.yaml command but annotate it as not wired in the current
  open-source analytical binary (flag not parsed; refer to earlier SimAI versions)
- Fix build-options parameter table (-busbw row) and the backwards busbw description sentence

[ZH]
- 将自动总线带宽命令(-nv/-nic/-n_p_s)提升为 analytical 的主/默认可运行示例,
  覆盖 README(EN/CN/JA)、build-options、Tutorial(EN/CN)
- 保留 -busbw example/busbw.yaml 示例,但备注其在当前开源 analytical 二进制中未接线
  (参数不解析;手动 busbw.yaml 用法请参考早期 SimAI 版本)
- 修正 build-options 参数表(-busbw 行)与描述句中与现实相反的表述
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Follow-up: analytical -busbw doc fix + verification / 后续:analytical -busbw 文档修复与验证

While testing the analytical mode I found the documented -busbw example/busbw.yaml command does not run. This commit makes the docs match the actual binary.

在测试 analytical 模式时发现文档里的 -busbw example/busbw.yaml 命令无法运行。本次提交让文档与实际二进制一致。

Static analysis / 静态分析

  • astra-sim-alibabacloud/astra-sim/system/AstraParamParse.hh has no -busbw parse branch (only -w/-g/-g_p_s/-r/-nv/-nic/-n_p_s/-nic_t/-g_type/-v/*_overlap/-l); there is no busbw.yaml reader anywhere.
  • The same is true on aliyun/SimAI master — so -busbw has never worked in the open-source analytical binary (a long-standing upstream doc issue, not introduced by this PR).
  • 结论:-busbw 从未被开源 analytical 二进制解析;自动档 -nv/-nic/-n_p_s 才是可用方式。

Dynamic test / 动态测试

Command Result
./bin/SimAI_analytical ... -r test- -busbw example/busbw.yaml FAIL — exit 255, only prints usage/help (flag unrecognized)
./bin/SimAI_analytical -w ./example/workload_analytical.txt -g 9216 -nv 360 -nic 48.5 -n_p_s 8 -g_p_s 8 -r example- PASS — exit 0, produced results/example-EndToEnd.csv (Total time 7,545,619)

Doc change / 文档改动

  • Promote the automatic-busbw command (-nv/-nic/-n_p_s) to the primary, runnable default in README (EN/CN/JA), docs[/CN]/configuration/build-options.md, and docs[/CN]/Tutorial.md.
  • Retain the -busbw example/busbw.yaml command and busbw.yaml section, annotated as not wired in the current open-source binary (refer to earlier SimAI versions).
  • 保留 -busbw/busbw.yaml 内容并加注"当前开源二进制未接线",将自动档设为默认可运行示例。

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