feat(allowlist): add Verilog, SystemVerilog, and VHDL support

[Parikalp-Bhardwaj]

Description

Implements the Hardware Description Language group requested in #470, adding support for Verilog, SystemVerilog, and VHDL.

Changes include:

• Allow .v, .sv, .vhd, and .vhdl files, including case-insensitive variants.
• Exclude conventional testbench files using:
  • **/tb_*.{v,sv,vhd,vhdl}
  • **/*_tb.{v,sv,vhd,vhdl}
• Map .v and .sv files to verilog.md.
• Map .vhd and .vhdl files to vhdl.md.
• Add language-specific review guidance for Verilog/SystemVerilog and VHDL.
• Add allowlist, exclusion, negative-boundary, and rule-resolution tests.

.v extension note

The .v extension is shared with the V programming language. Following the Hardware Description scope in #470, this change treats .v as Verilog. The current resolver uses file extensions and cannot distinguish the two languages by content.

Type of Change

• Bug fix (non-breaking change that fixes an issue)
• New feature (non-breaking change that adds functionality)
• Breaking change (fix or feature that would cause existing functionality to change)
• Refactoring (no functional changes)
• Documentation update
• CI / Build / Tooling

How Has This Been Tested?

• make test passes locally
• Manual testing (describe below)

Additional verification:

• go test ./internal/config/allowlist/... ./internal/config/rules/... -count=1
• make check
• make test

All commands pass locally.

Checklist

• My code follows the project's coding style (go fmt, go vet)
• I have performed a self-review of my code
• I have added tests that prove my feature works
• New and existing unit tests pass locally with my changes
• I have updated the documentation accordingly
• I have signed the CLA

Related Issues

Closes #1049
Part of #470

[CLAassistant]

All committers have signed the CLA.

[github-actions]

✅ OpenCodeReview: Review complete: 0 finding(s) across 3 selected item(s).

[lizhengfeng101]

@Parikalp-Bhardwaj Thank you for your submission! We really appreciate it. Like many open source projects, we ask that you sign our Contributor License Agreement before we can accept your contribution.

[Parikalp-Bhardwaj]

Hi @lizhengfeng101, thank you for reviewing my submission. I have completed and signed the Contributor License Agreement.

[wu21-web]

Please update the documentation. Your desc marked this as completed, but no site documentation updated.
Why do agents forget this every time 🤔

[wu21-web]

The wiring is complete (including exclude patterns), the documentation has some problems however.

[Parikalp-Bhardwaj]

Thank you for the detailed review. I’ve updated the Verilog/SystemVerilog and VHDL rule documentation to address all the points raised, including case completeness, edge detection, typing and resizing semantics, procedural assignments, and tool-dependent synthesis support.

[lizhengfeng101]

merge conflicts @Parikalp-Bhardwaj

[Parikalp-Bhardwaj]

Hi @lizhengfeng101 I have resolved the merge conflicts, please review it when you have a chance. Thank you

[lizhengfeng101]

Checked the branch out and verified behavior rather than only reading the diff — case-insensitive chain, ordering, and the two test packages all pass. Three things:

1. Test name doesn't match its data. subtract has no tb substring (it's b+t). rtl/outbound.v does, and I verified it's still false:

-{"hdl tb substring mid-name not excluded", "rtl/subtract.v", false},
+{"hdl tb substring mid-name not excluded", "rtl/outbound.v", false},

2. .vh is missing (IsAllowedExt(".vh") == false). Verilog headers hold the `define macros and parameter/width constants — exactly what this rule doc targets. No collision, and I verified **/*.vh doesn't match .vhd/.vhdl:

-    "**/*.{v,sv}": "verilog.md",
+    "**/*.{v,vh,sv}": "verilog.md",

Plus ".vh" in supported_file_types.json, two allowlist cases, one resolve case, and the 4 doc tables. Exclude patterns need no change.

3. The .v collision is acknowledged but not mitigated. Coq/V files that were skipped as unsupported_ext now get reviewed with RTL guidance. One line in verilog.md, continuing the existing "Account for whether the file is synthesizable design code..." sentence, fixes it with no code:

The .v extension is also used by Coq and by the V language; if the file is not Verilog or SystemVerilog, report nothing HDL-specific and fall back to general review principles.

[Parikalp-Bhardwaj]

Thanks for the helpful review. I’ve addressed all three points:

• Replaced the misleading subtract.v test fixture with outbound.v.
• Added .vh support to the allowlist, rule mapping, tests, and documentation.
• Added guidance for handling .v files that contain Coq or V language code.

I also verified the changes with the focused Go tests, make check, make test, and the documentation typecheck and build. All checks pass locally.

Hopefully it will stay conflict-free this time!

[lizhengfeng101]

Thanks for the helpful review. I’ve addressed all three points:

• Replaced the misleading subtract.v test fixture with outbound.v.
• Added .vh support to the allowlist, rule mapping, tests, and documentation.
• Added guidance for handling .v files that contain Coq or V language code.

I also verified the changes with the focused Go tests, make check, make test, and the documentation typecheck and build. All checks pass locally.

Hopefully it will stay conflict-free this time!

merge conflicts ......

[Parikalp-Bhardwaj]

I can see that the conflicts were caused by the recently added solidity and vyper entries in main, since they modify the same allowlist and rule-mapping files as this PR 😅

[wu21-web]

Tip

Moving your insertions away from the end of any map, JSON gets you less merge conflicts.

[Parikalp-Bhardwaj]

@wu21-web The conflicts are now resolved and the updated branch has been pushed.

Tip

Moving your insertions away from the end of any map, JSON gets you less merge conflicts.

Good point, thanks for the tip. I kept the HDL entries before the existing solidity/vyper entries when resolving the conflicts, so hopefully the same overlap won’t happen again.

[lizhengfeng101]

Nit: pages/src/content/docs/ko/review-rules.md has the same rule table but wasn't updated — please add the Verilog/VHDL rows there as well.