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@MicrosoftCopilot @Argus-AiTeam

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aHappend/README.md

Hi, I'm Sufeng Guo

Undergraduate at Nanjing University (VLSI Design & System Integration), graduating in 2027.

I work on autonomous AI systems, AI accelerators, computer architecture, and hardware-software co-design.

Personal website: ahappend.github.io

Education & Experience

  • Nanjing University — VLSI Design & System Integration
  • Campus locations: Nanjing (Year 1); Suzhou (Years 2–4)
  • Expected graduation: 2027
Period Experience
Sep–Dec 2026 Microsoft Research Asia (MSRA) — Research Intern, Systems Research Group, Beijing. Group website ↗
Jan–May 2027 Nanyang Technological University (NTU), Singapore — Government-Sponsored Visiting Undergraduate. Program website ↗

Interests

Autonomous AI DNN Mapping Scheduling NoC RTL Edge AI Reproducible Systems

Currently Working On

  • Native AWQ W4A16 and mixed-precision RTL for transformer inference
  • DNN mapping and inter-layer scheduling for tiled accelerators
  • Hardware-software co-design for AI accelerators
  • Evidence-driven autonomous research and engineering systems

Projects

  • Argus/original / ArgusAgent/Microsoft — Open multi-agent runtime for long-horizon research and engineering, combining persistent state, reviewed execution, verification, and evidence. Technical report ↗
  • ACE-3/personal / ACE-3/organization — Argus-built, evidence-first Qwen2.5-0.5B-Instruct-AWQ W4A16 RTL with a verified 24-layer cascade and authenticated Hybrid RTL runtime.
  • ACE-2/personal / ACE-2/organization — Argus-built Qwen2.5-0.5B W4A8 accelerator with SystemVerilog RTL, certified two-token integration, SKY130 100 MHz results, and evidence-first host-trust recovery.
  • 64-Point FFT — Resource-efficient radix-2 DIT FFT in SystemVerilog using folded streaming SDF RTL, Q1.15 fixed-point arithmetic, Vivado/XSim simulation, Python/NumPy co-verification, and Virtex-7 implementation results.
  • Two-Stage CMOS Op-Amp — Two-stage CMOS operational amplifier in TSMC 0.18 μm technology, with Miller compensation and Spectre AC/DC/transient verification.

Publications

Research Profiles

Tools

Python C/C++ TypeScript SystemVerilog Verilog React Linux

Contact

Popular repositories Loading

  1. ace-2 ace-2 Public

    Argus-built, evidence-first Qwen2.5-0.5B W4A8 accelerator: certified two-token RTL integration, SKY130 100 MHz, and Fresh-L2-accepted V8 host-trust recovery.

    SystemVerilog 1 1

  2. 64-point-fft-hardware 64-point-fft-hardware Public

    Resource-efficient 64-point radix-2 DIT FFT in SystemVerilog: folded streaming SDF RTL, Q1.15 fixed-point arithmetic, Vivado/XSim simulation, Python/NumPy co-verification, and Virtex-7 implementati…

    C

  3. SET-NN-Mapping-Scheduling SET-NN-Mapping-Scheduling Public

    Exploring the impact of neural network task granularity on mapping and scheduling efficiency on multi-core NoC architectures based on the SET framework.

  4. Crane Crane Public

    Independent Python reproduction of Crane (MICRO 2025): real network DAGs, checked ScT/MeT scheduling, native SET core profiles, reproducible experiments and an offline interactive demo.

    Python

  5. two-stage-cmos-op-amp two-stage-cmos-op-amp Public

    Two-stage CMOS operational amplifier designed in TSMC 0.18 um technology, with Spectre AC/DC/transient verification, Miller compensation, and analysis of gain, bandwidth, phase margin, slew rate, o…

    TeX

  6. aHappend aHappend Public

    Sufeng Guo - personal profile