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F3 port + F4 OC3PE knob with 35-run frequency bench - #38

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a5021 merged 4 commits into
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feature/f3-stm32f303
Sep 30, 2026
Merged

a5021 merged 4 commits into
mainfrom
feature/f3-stm32f303

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@a5021 a5021 commented Sep 30, 2026

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What

  • F3 (STM32F303RE) port: shared F0/F1/G0 core + F3 backend plugs in via the same sixteen functions; family-specific facts now live in the port headers, one family chain. Includes F3 clock-failure flag generalization and ow_stats F3 dispatch.
  • F4: sweepable OC3PE output-compare preload knob (default on), plus a hardened object-name stamp that folds EXT into it.
  • Benches (hardware-verified):
Bench Result
F3 7 apps x 8/64/72 MHz 21/21 PASS
F4 OC3PE sweep OC3PE=1 7/7 sensors ~21 C, OC3PE=0 stalls (load-bearing, stays on)
F4 7 apps x 180/168/84/16/8 MHz 35/35 PASS

Key notes

  • F3 has no HSI16 and PLLMUL <= 16 -> structural 64 MHz ceiling, documented in the clock-failure banner.
  • OC3PE preload is load-bearing on F4; the default-on machine code is unchanged.
  • Makefile now appends a sanitised EXT to OBJ_STAMP; without it a rebuild with different -D flags silently reused stale objects (the OC3PE sweep was initially poisoned by exactly this).

Docs

docs/bench/f3-2026-09-29/, docs/bench/f4-2026-09-30/ (logs + LA captures).

Step A of the port-layer review: kill the treble duplication of family
selection (onewire.h token chain + ow_port.h re-pick + per-family block).

- inc/onewire.h: one OW_PORT_FAMILY chain and one #include branch that
  pulls the selected backend directly, with #error on no family; the
  HSE/F4_MAX/SYSCLK/IRQn facts block and ow_pulse_t typedef are gone.
- port/ow_port_fX.h: own their facts (ow_pulse_t, OW_PORT_SYSCLK_MHZ,
  OW_HSE_MHZ where the family has one, OW_PORT_F4_MAX_SYSCLK_MHZ on F4,
  OW_PORT_TIM1_UPD_IRQn under OW_PORT_LOW_POWER), so backend and defaults
  cannot drift; includes ow_port.h after the facts.
- inc/ow_port.h: no backend selection (onewire.h did it), optional
  OW_PORT_MARKER_TOGGLE() hook defaulting to empty, capture-width comment
  covering both the basic-DMA (PSIZE=16+MSIZE=8) and F4 direct
  (PSIZE=MSIZE=8) semantics; IC4F ladder moved out (see below).
- port/common/ow_port_tim_dma.h: IC4F ladder lives here next to the
  prescaler that reads it, so it is in scope before any TIM_CCMR2(...,OW_PORT_IC4F_ARGS)
  in every include order - fixing the standalone-ow_port.h TU failure
  ('TIM_CCMR2_OW_PORT_IC4F_ARGS' undeclared) that the old ow_port.h-first
  placement caused; the five required backend macros and both DMA channel
  defines now get checked with #error after the include guard.
- port/stm32f4/ow_port_f4.h: identical IC4F ladder (it does not include
  the core), assert(0) reject paths -> clean returns, <assert.h> dropped,
  and the three CCR3 preloads plus the trailing-feed entry spelled as
  ONEWIRE_RELEASE_PULSE instead of a bare 0.
- examples/app, tests, CMakeLists comments follow the refactor; ci.yml
  cppcheck now passes -Iport/* exactly as the build tree exports them, so
  the static-analysis include contract matches the headers that own the
  facts.

Verified: host tests + ndebug/lowpower/active variants for all five
families, test-mocks, clang-format --dry-run, cppcheck x6 all green, and
the ds18b20_1_basic .bin for f0/f1/g0/f3/f4 rebuilds byte-identical to
the pre-refactor baseline.
@a5021
a5021 merged commit d47523c into main Sep 30, 2026
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@a5021
a5021 deleted the feature/f3-stm32f303 branch September 30, 2026 17:10
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