amd: seed atomic RMW as divergent - #150
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atomicAdd (and the rest of the atomic RMW family) returns the pre-op value
seen by *this lane* — even with a uniform address and operand, lanes
serialise on the atomic and each gets a different old value back. The
isel already puts the result in a VGPR, but divergence_analysis was
missing the seed, so a downstream GEP off the atomic result took the
scalar path in isel_gep and emitted s_add_u32 with a VGPR source. The
verifier caught it as "VGPR in scalar source"; hardware would just
fault.
Seed BIR_ATOMIC_{ADD,SUB,AND,OR,XOR,MIN,MAX,XCHG,CAS} alongside
BIR_THREAD_ID and BIR_SHFL_*. ATOMIC_LOAD stays out (uniform if the
address is uniform, propagation handles the rest); ATOMIC_STORE has
no result to track.
Unblocks per-thread SYSPRINT on AMD. Docs and the launcher comment
were carrying the "AMD path currently trips a regalloc bug" caveat,
which is no longer true.
Zaneham
added
the
backend: AMD
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The AMD divergence analysis wasn't seeding
BIR_ATOMIC_*RMW ops as divergent, so a GEP off anatomicAddresult took the scalar path inisel_gepand emitteds_add_u32with a VGPR source. The verifier caught it; hardware would just fault. This is the "AMD path currently trips a regalloc bug on the byte-copy loop" note indocs/mainframe.mdandexamples/launch_sysprint.c, both cleared here.Seeds
BIR_ATOMIC_{ADD,SUB,AND,OR,XOR,MIN,MAX,XCHG,CAS}alongsideBIR_THREAD_IDand the shuffles.ATOMIC_LOADandATOMIC_STOREdon't need seeding. Per-thread SYSPRINT now compiles clean on AMD; test suite unchanged (347/11/1 before and after).Not GPU-executed on my end (no HSA runtime on this Windows box). Verifier's
vfy_sopis check #1 for exactly this class, so it's a strong proxy, but the actual hardware run is worth doing before merging.