target/riscv: Add Sscpuutil (CPU Utilization) extension emulation#13
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Estherrzhang wants to merge 1 commit into
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target/riscv: Add Sscpuutil (CPU Utilization) extension emulation#13Estherrzhang wants to merge 1 commit into
Estherrzhang wants to merge 1 commit into
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Add emulation for the RISC-V Sscpuutil extension which provides CPU utilization counters: corecyc (0xc30) counts core cycles at actual frequency, acttime (0xc31) counts active time at a fixed reference rate. Includes M-mode variants (mcorecyc/macttime at 0xb30/0xb31), access control CSRs (mcpuutilen/scpuutilen/hcpuutilen), and the full privilege access control chain (M->S, S->U, H->VS). Also adds clock-frequency DT property to virt machine CPU nodes for kernel FIE (Frequency Invariance Engine) support. Signed-off-by: Esther Z <zhangfengxue.zfx@alibaba-inc.com>
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Add emulation for the RISC-V Sscpuutil extension which provides CPU utilization counters: corecyc (0xc30) counts core cycles at actual frequency, acttime (0xc31) counts active time at a fixed reference rate.
Includes M-mode variants (mcorecyc/macttime at 0xb30/0xb31), access control CSRs (mcpuutilen/scpuutilen/hcpuutilen), and the full privilege access control chain (M->S, S->U, H->VS).
Also adds clock-frequency DT property to virt machine CPU nodes for kernel FIE (Frequency Invariance Engine) support.