Fix ISD2115 write skipping and RP2040 unaligned memory access#63
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notexactlynikhil wants to merge 1 commit into
Open
Fix ISD2115 write skipping and RP2040 unaligned memory access#63notexactlynikhil wants to merge 1 commit into
notexactlynikhil wants to merge 1 commit into
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Summary of Changes
This PR resolves writing/verification failures on the ISD2115 (and potentially other ISD/Nuvoton voice chips) by fixing a PIO timing race condition and resolving a silent unaligned memory access bug on the Cortex-M0+ core.
Root Causes & Fixes
1. ISD SPI Byte Skipping (PIO Race Condition)
spi.pio, the CPHA1 SPI program (spi_cpha1_cs) loops back and checks theRDYpin (wait 1 GPIO 11) immediately after transmitting a byte. Since the PIO clock is running at 4MHz, it executes this check before the ISD chip can physically pull theRDYpin low (busy). Consequently, the PIO incorrectly assumes the chip is ready and immediately transmits the next byte, causing the ISD chip to skip every alternating byte. The ISD2110 barely squeaked by this timing margin, while the ISD2115 consistently failed.[31], ~7.75µs) on the loopback jump instruction inspi.pio(jmp !osre byteloop side 0x0 [31]). This gives the chip adequate time to pullRDYlow, ensuring the subsequentwaitblocks correctly until the chip is ready for the next byte.2. Silent Command Corruption (Cortex-M0+ Unaligned Store)
isd1200.c(isd1200_flash_readandisd1200_flash_write), the 24-bit offset was written using a 32-bit pointer dereference at an unaligned address:*(uint32_t *)&buf[1] = __builtin_bswap32(offset << 8);. On the RP2040's Cortex-M0+ core, unaligned 32-bit stores are not supported and are silently aligned down to the nearest 4-byte boundary. This resulted in the write targetingbuf[0], corrupting the command byte (e.g.,CMD_DIG_WRITE/0xA0).buf[1],buf[2], andbuf[3].File Modifications
[31]delay cycles to CPHA1 SPI loopback to preventRDYpin race condition.Verification & Testing