SystemVerilog FSM-Based Intelligent Traffic Management System
Pedestrian Crossing • Emergency Vehicle Priority • GTKWave Verification • Streamlit Dashboard
🔗 Live Dashboard
https://fpga-smart-traffic-light-controller-74fyvkmvcljtrogolskfap.streamlit.app/
The FPGA Smart Traffic Light Controller is a SystemVerilog-based Finite State Machine (FSM) project designed to manage traffic flow efficiently and safely at a road intersection.
This controller incorporates:
✅ North-South and East-West Traffic Control
✅ Pedestrian Crossing Support
✅ Emergency Vehicle Priority Override
✅ Safe All-Red Transition States
✅ GTKWave Verification
✅ Interactive Streamlit Dashboard
The project demonstrates practical concepts in:
- FPGA Design
- RTL Development
- FSM Modeling
- Digital Logic Design
- Verification Engineering
- Traffic Management Systems
- North-South Traffic Sequencing
- East-West Traffic Sequencing
- Timer-Based State Transitions
- Safe Traffic Coordination
- Pedestrian Request Button
- Dedicated Pedestrian Walk State
- Safe All-Red Transition
- Automatic Return to Traffic Flow
- Emergency Detection Input
- Immediate Priority Access
- Traffic Override Functionality
- Safe Recovery Mechanism
- Real-Time Dashboard
- Traffic State Visualization
- Traffic Analytics
- Event Monitoring
- Verification Reports
| Signal | Description |
|---|---|
| clk | System Clock |
| rst | System Reset |
| ped_button | Pedestrian Crossing Request |
| emergency | Emergency Vehicle Detection |
| Signal | Description |
|---|---|
| NS_G | North-South Green |
| NS_Y | North-South Yellow |
| NS_R | North-South Red |
| EW_G | East-West Green |
| EW_Y | East-West Yellow |
| EW_R | East-West Red |
| State | Description |
|---|---|
| NS_GREEN | North-South Green |
| NS_YELLOW | North-South Yellow |
| ALL_RED_1 | Safety Transition State |
| PED_WALK | Pedestrian Walk State |
| EW_GREEN | East-West Green |
| EW_YELLOW | East-West Yellow |
| ALL_RED_2 | Safety Transition State |
| EMERGENCY_GREEN | Emergency Priority State |
NS_GREEN
↓
NS_YELLOW
↓
ALL_RED_1
↓
PED_WALK
↓
EW_GREEN
↓
EW_YELLOW
↓
ALL_RED_2
↓
NS_GREEN
ANY_STATE
↓
EMERGENCY_GREEN
↓
NS_GREEN
FPGA-Smart-Traffic-Light-Controller
│
├── rtl/
│ └── traffic_fsm.sv
│
├── tb/
│ └── traffic_tb.sv
│
├── constraints/
│ └── traffic_constraints.xdc
│
├── scripts/
│ ├── compile.bat
│ ├── simulate.bat
│ ├── open_waveform.bat
│ └── run_all.bat
│
├── dashboard/
│ ├── app.py
│ ├── traffic_data.csv
│ └── requirements.txt
│
├── waveforms/
│ ├── traffic.vcd
│ └── waveform_analysis.md
│
├── reports/
│ └── simulation_report.md
│
├── docs/
│ └── project_report.pdf
│
├── images/
│ ├── github_banner.png
│ ├── architecture.png
│ ├── fsm_diagram.png
│ ├── dashboard.png
│ ├── traffic_waveform.png
│ ├── pedestrian_waveform.png
│ └── final_waveform.png
│
├── README.md
├── LICENSE
├── requirements.txt
└── .gitignore
iverilog -g2012 -o traffic.out rtl/traffic_fsm.sv tb/traffic_tb.svvvp traffic.outgtkwave traffic.vcd- NS_GREEN
- NS_YELLOW
- EW_GREEN
- EW_YELLOW
- ALL_RED States
The waveform confirms proper timer-based sequencing and safe traffic signal transitions.
- Pedestrian Button Detection
- Safe Traffic Halt
- Dedicated PED_WALK State
- Automatic Traffic Recovery
The controller successfully processes pedestrian requests without compromising traffic safety.
- clk
- rst
- current_state
- next_state
- timer_count
- ped_button
- emergency
- NS_G
- NS_Y
- NS_R
- EW_G
- EW_Y
- EW_R
| Test Case | Result |
|---|---|
| Reset Functionality | ✅ PASS |
| NS Green Operation | ✅ PASS |
| NS Yellow Operation | ✅ PASS |
| Pedestrian Request | ✅ PASS |
| Pedestrian Walk State | ✅ PASS |
| EW Green Operation | ✅ PASS |
| EW Yellow Operation | ✅ PASS |
| Emergency Override | ✅ PASS |
| Emergency Recovery | ✅ PASS |
| FSM Recovery | ✅ PASS |
- Live Traffic Monitoring
- Signal Status Tracking
- Pedestrian Analytics
- Emergency Event Monitoring
- Traffic Statistics
- FSM State Tracking
- Traffic Visualization
- Smart Cities
- Intelligent Transportation Systems
- Urban Traffic Management
- Emergency Response Networks
- FPGA-Based Controllers
- Embedded Systems
- VLSI Design Projects
- Academic Research
- Vehicle Density Detection
- Adaptive Signal Timing
- AI-Based Traffic Optimization
- IoT Traffic Monitoring
- Multi-Junction Synchronization
- Camera-Based Traffic Analysis
- FPGA Hardware Deployment
- Cloud-Based Traffic Analytics
- FPGA Design Methodology
- RTL Design
- FSM Modeling
- SystemVerilog
- Python
- Icarus Verilog
- GTKWave
- Streamlit
- Pandas
- Plotly
Detailed project documentation is available in:
docs/project_report.pdf
Additional reports:
reports/simulation_report.md
waveforms/waveform_analysis.md
B.Sc Digital & Cyber Forensic Science
🔗 GitHub: https://github.com/VaishnavaDevi-R
🔗 LinkedIn: https://www.linkedin.com/in/vaishnava-devi-141142321/
🔗 Instagram: https://www.instagram.com/_vaishforge_/
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This project is licensed under the MIT License.
See the LICENSE file for more information.






