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Allow passing custom module name to output_to_verilog#474

Merged
fdxmw merged 12 commits into
UCSBarchlab:developmentfrom
devmam999:feature/module_name_param
Nov 17, 2025
Merged

Allow passing custom module name to output_to_verilog#474
fdxmw merged 12 commits into
UCSBarchlab:developmentfrom
devmam999:feature/module_name_param

Fixed formatting errors

c252752
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