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Opt in first 8 designs to use 'syn' #4270
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1b1b495
Add option of synthesis using 'syn'
povik ca84ff7
Opt in first 8 designs to use 'syn'
povik c298a08
Streamline metrics emission for synth stage
povik a3bec38
Relax gcd-ccs metrics for syn switch
povik ebd94d5
flow: update rules
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| Original file line number | Diff line number | Diff line change |
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@@ -18,4 +18,4 @@ export ASAP7_USE_VT = LVT | |
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| export RECOVER_POWER = 100 | ||
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| export SYNTH_USE_SYN = 1 | ||
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| Original file line number | Diff line number | Diff line change |
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@@ -16,3 +16,4 @@ export PLACE_DENSITY = 0.35 | |
| # few last gasp iterations | ||
| export SKIP_LAST_GASP ?= 1 | ||
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| export SYNTH_USE_SYN = 1 | ||
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| Original file line number | Diff line number | Diff line change |
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@@ -15,3 +15,4 @@ export PLACE_DENSITY = 0.75 | |
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| export TNS_END_PERCENT = 100 | ||
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| export SYNTH_USE_SYN = 1 | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
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@@ -18,3 +18,4 @@ export RECOVER_POWER = 100 | |
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| export ASAP7_USE_VT = LVT | ||
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| export SYNTH_USE_SYN = 1 | ||
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| Original file line number | Diff line number | Diff line change |
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@@ -14,3 +14,5 @@ export TNS_END_PERCENT = 100 | |
| export USE_FILL = 1 | ||
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| export REMOVE_ABC_BUFFERS = 1 | ||
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| export SYNTH_USE_SYN = 1 | ||
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In the new
synsynthesis flow (SYNTH_USE_SYN=1), the1_synthtarget does not list$(VERILOG_FILES)or$(SDC_FILE)as dependencies. This breaks incremental builds, as modifying any Verilog source files or timing constraints will not trigger a re-synthesis of the design. Please add them to the dependency list.