Carriage 3: LayoutAssignmentPass on the production path — one target, one decision

[michalharakal]

Closes #1180 (parent #1147, carriage slice 3 of 3). Stacked on #1183 — merge order: #1183 → this ("delete branch" each time and the retarget is automatic).

The optimizer pipeline joins the production tape→HLO path, and the first real layout decision runs on it.

• HloGenerator.generate(target: String? = null) — null (the default) runs no pipeline and emits byte-identically to before (pinned: no order is invented without a pass); a named target runs dagPipelineFor(target) with LayoutAssignmentPass as a core pass, plus whatever the target registered through TargetOptimizers — the registry that existed since [S0.9] Golden parity gate + PR gate script + benchmark baseline (guards every memory-architecture slice) #1005 and was never on the production path until now. compile-hlo gains the compile-opt dependency this wiring always implied (opt→dag, no cycle).
• LayoutAssignmentPass, deliberately narrow: rank-2 block-quantized weights (the GGML block formats) get kernel-feed order (INPUT_BLOCK_MAJOR), mirroring the decision the eager form resolver makes at load (Packed storage that knows its own block order, so KERNEL_FEED can reach a kernel #1120) — and the tape's carried fact always outranks the pass's preference (a loader-declared ROW_MAJOR is never overridden). Touched nodes are stamped with the backend assignment.
• The pre-built ResolvedComputeGraph seams stop returning hardcoded null: resolvedLayout derives BlockOrderLayout from what the passes (or the tape) stamped; backendAssignment reads node metadata whose key lives on ResolvedComputeGraph — imported by the pass along the legal opt→dag direction.
• The known traps are dodged by design: fusion stays un-enabled (only the layout pass runs as core), Minerva stringification is moot (block order is already a string), and no sk.ainet.lang.memory import entered skainet-compile.
• Tests: pass semantics (decides / never overrides / leaves dense & rank-1 alone; seams surface exactly the decisions made) and the pipeline→emission composition (a decided order reaches the module header as block_order = "INPUT_BLOCK_MAJOR").

With this merged, all three carriage slices are in and #1147 can close — leaving #1148 as the placeholder for the IREE-validation SKEEP per the agreed strategy (conformity via SKaiNET-transformers, post-release).

Full pr-gate green.

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