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[Export] Align graph export architecture for StableHLO and Minerva #687

Description

@michalharakal

Goal

Add Minerva as a secure MCU export backend while aligning the export architecture with the existing StableHLO conversion model.

Architecture direction

Use ComputeGraph as the shared export boundary.

Create a common graph-export workflow where StableHLO and Minerva share:

  • graph validation entry points
  • conversion context concepts
  • registry/factory structure
  • structured diagnostics
  • result objects suitable for downstream packaging or writing

Keep backend writers separate:

  • StableHLO writer emits MLIR text through operation converters.
  • Minerva writer emits a Minerva intermediate model, .npz compiler input, compiler artifacts, and a packaged host/firmware project.

Phase-one Minerva scope

  • JVM host support
  • Sequential MLP models only
  • Static shapes only
  • Q8 Minerva compiler flow
  • Host verification before reporting export success
  • Clear secret-handling boundaries for generated artifacts

Out of scope for phase one

  • Conv1D export
  • BNN export
  • In-process Minerva compiler rewrite
  • Hardware-in-the-loop CI
  • Support for arbitrary MCU targets beyond validated Minerva target configs

Definition of done

  • Supported SKaiNET MLP graphs export to a Minerva project bundle.
  • The export flow generates compiler input, weights.c, weights.h, manifest, host harness, firmware example, and documentation.
  • Unsupported graphs fail before compiler invocation with actionable compatibility diagnostics.
  • Host validation runs in CI without MCU hardware.
  • Existing StableHLO conversion keeps working while the shared graph-export contracts are introduced incrementally.

Activity

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