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An FP16 LayerNorm computes variance as a mean over 1280 squared, centred activations. For real Whisper encoder activations the sum exceeds the FP16 maximum before the division, variance becomes +Inf, rsqrt becomes 0, and the block silently emits zeros for those frames — 6 of 1500 frames in the measured case, enough to drop encoder cosine from 0.9999 to 0.968. The fix on the LiteRT side was a graph rewrite ((0.25·δ)² · 16) because the runtime offered no lever.
SKaiNET will meet the same bug the moment an FP16 GPU or NPU lowering exists. It should be reproducible on a desktop CPU before that, so the lowering rule (accumulate variance in FP32, or apply the rescale) can be written and regression-tested against a known-failing input.
Scope
Fp16SimulationExecutionContext (or a DirectCpuExecutionContext option): after every op, round the output through Fp16Codec (round-to-nearest-even, overflow to ±Inf, gradual underflow) — storage-only simulation. A second mode also rounds accumulators inside reductions (sum/mean/variance/matmul) to model true half-precision arithmetic.
A regression test with a synthetic [1500,1280] input scaled so that naive FP16 variance overflows, asserting +Inf under accumulate-in-half and a finite, correct value under the FP32-accumulate lowering.
layerNorm lowering rule for FP16 targets in skainet-compile-hlo: variance reduction in F32 (or the documented rescale), with a TraceEvent naming which rule fired.
Docs: an explanation page on narrow-float numerics pitfalls with this as the worked example.
Acceptance
The overflow reproduces in a unit test on a JVM with no GPU.
Context
An FP16 LayerNorm computes variance as a mean over 1280 squared, centred activations. For real Whisper encoder activations the sum exceeds the FP16 maximum before the division, variance becomes +Inf, rsqrt becomes 0, and the block silently emits zeros for those frames — 6 of 1500 frames in the measured case, enough to drop encoder cosine from 0.9999 to 0.968. The fix on the LiteRT side was a graph rewrite (
(0.25·δ)² · 16) because the runtime offered no lever.SKaiNET will meet the same bug the moment an FP16 GPU or NPU lowering exists. It should be reproducible on a desktop CPU before that, so the lowering rule (accumulate variance in FP32, or apply the rescale) can be written and regression-tested against a known-failing input.
Scope
Fp16SimulationExecutionContext(or aDirectCpuExecutionContextoption): after every op, round the output throughFp16Codec(round-to-nearest-even, overflow to ±Inf, gradual underflow) — storage-only simulation. A second mode also rounds accumulators inside reductions (sum/mean/variance/matmul) to model true half-precision arithmetic.[1500,1280]input scaled so that naive FP16 variance overflows, asserting+Infunder accumulate-in-half and a finite, correct value under the FP32-accumulate lowering.layerNormlowering rule for FP16 targets inskainet-compile-hlo: variance reduction in F32 (or the documented rescale), with aTraceEventnaming which rule fired.Acceptance
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