This project measures the memory latency of a RISC-V board by evolving a benchmark through three strategies, each one improving upon the last.
This simple approach creates a completely random pointer chain within a buffer. It then measures the average time taken for each memory access while traversing this chain. This method is a common starting point for memory benchmarking.
This plot shows the rough cache sizes but is very noisy for larger buffers. For buffer sizes < L1 sizes we get accurate L1 access latency around 5ns, for L2 the latency is mix of L1 and L2 accesses, and for sizes > L2 the access latency is mix of L1,L2 and DRAM access latencies.
This strategy uses a smarter access pattern that jumps between different cache lines. It is designed to intentionally miss the L1 cache when the L1 < buffer size < L2 but and misses both L1 and L2 for sizes > L2, so it purely measures the L1, L2 and DRAM access latency average.
This result is much cleaner, showing a clear, flat plateau for the L2 cache latency and DRAM access.
The previous strategies did'nt account for the TLB misses, normally the page table size is 4KB , so when buffer size is greater than number of PTE entries L1 TLB can store we get miss between them due to our random access all over the pages more than once. That's why the the three lines were not completely flat for each hirarchy. We are using huge page tables of 2MB available in sv39 of riscv. Now we are reducing the page tables misses and latency lines are more flat now, which means less noise.
This plot is nearly perfect, showing stable, flat lines for each memory level. It clearly reveals the true, isolated latency of the L1, L2, and DRAM.
| Memory Level | Size | Latency |
|---|---|---|
| L1 Data Cache | 32 KB | ~8 cycles |
| L2 Cache | 512 KB | ~45 cycles |
| DRAM | N/A | ~350 cycles |