RISCY-Lib is an opensource collection of RTL (mainly SystemVerilog) design and verification Tools.
A single repo with a collection of all the currently supported agents can be found: here
- ahb_agent
- A UVM Agent for the AHB Interface
- apb_agent
- A UVM Agent for the APB Interface
- axi_stream_agent
- A UVM Agent for the AXI-Stream Interface
- spi_agent
- A UVM Agent for SPI devices w/ support for UVM-MS
- uart2sram
- A module which converts the UART2Register Packet to an SRAM interface
