Skip to content

[axi-qspi/dv] Add behavioral QSPI flash model and top-level integration (Part 1/3) - #2

Open
Raghavan-04 wants to merge 1 commit into
OpenCoreLabsX:mainfrom
Raghavan-04:dv/qspi-flash-model
Open

[axi-qspi/dv] Add behavioral QSPI flash model and top-level integration (Part 1/3)#2
Raghavan-04 wants to merge 1 commit into
OpenCoreLabsX:mainfrom
Raghavan-04:dv/qspi-flash-model

Conversation

@Raghavan-04

Copy link
Copy Markdown

Summary

Adds a behavioral QSPI flash memory model (uvm/tb/qspi_flash_model.sv) and integrates it into the top-level testbench (uvm/tb/axi_qspi_tb_top.sv) across the external bidirectional SPI pins. This establishes the physical slave endpoint necessary to verify memory-mapped reads, dummy cycles, mode-byte decode, and XIP fast-path transfers. Also resolves host-specific executable paths in the Makefile and documents flash preloading methods in the README.md.

Related issue or proposal

Related to #1 (Part 1/3: Behavioral Flash Model & Top-Level Hookup)

Design notes

  • Command & Protocol Decoding: Implements SPI command decoding for Standard Read (0x03), Fast Read (0x0B), Dual Output Read (0x3B), Quad Output Read (0x6B), and Quad I/O Read (0xEB).
  • Continuous Read Mode: Decodes mode byte 0xA0 during Quad I/O transactions, allowing subsequent transactions to skip the 8-bit command phase and transition directly to address nibbles.
  • I/O Ownership & Timing: Tri-state bidirectional control on io[3:0]. Keeps lines High-Z during input phases (CMD, ADDR, MODE, DUMMY) and drives read data on negedge sclk with proper sampling on posedge sclk.
  • Memory Preloading: Provides a byte-addressable internal memory array initialized by default to i[7:0] ^ 8'hA5, configurable via MEM_INIT_FILE parameter ($readmemh) or dynamic runtime task load_mem_file().
  • Portability: Sanitized Makefile tool definitions (VERILATOR_BIN, UVM_HOME) to remove hardcoded Windows paths, ensuring compatibility with Linux containers and CI environments.

Verification

  • RTL & Model Lint Check:
make lint

Result: Clean compilation with 0 errors and 0 warnings.

  • Strict Model Lint Check:
verilator --language 1800-2017 -Wall -Wno-TIMESCALEMOD -Wno-EOFNEWLINE --lint-only uvm/tb/qspi_flash_model.sv

Result: Passed with 0 warnings.

Protocol & Timing Smoke Test:
Ran a cycle-accurate self-checking simulation verifying:

  • Standard Read (0x03) at 0x000000 (received 0xA5)
  • Fast Read (0x0B) with 8 dummy clocks at 0x000004 (received 0xA1)
  • Quad I/O Read (0xEB) with 4 dummy clocks + Mode 0xA0 at 0x000010 (received 0xB5)
  • Continuous Quad Read bypassing the command opcode at 0x000020 (received 0x85)
    Result: >>> ALL 4 FLASH PROTOCOL SMOKE TESTS PASSED! <<<

Checklist

  • Scope was discussed before implementation when required.
  • RTL is synthesizable and follows the repository style.
  • Reset, errors, backpressure, and corner cases were considered.
  • [] Tests fail without the fix where this is a bug fix.
  • [] UVM/assertions/coverage were updated where applicable.
  • Lint, compile, simulation, and relevant regressions pass.
  • Documentation and register descriptions are current.
  • Commits are focused, atomic, and free of unrelated changes.
  • New code is original or correctly licensed and attributed.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant