[axi-qspi/dv] Add behavioral QSPI flash model and top-level integration (Part 1/3) - #2
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[axi-qspi/dv] Add behavioral QSPI flash model and top-level integration (Part 1/3)#2Raghavan-04 wants to merge 1 commit into
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Summary
Adds a behavioral QSPI flash memory model (
uvm/tb/qspi_flash_model.sv) and integrates it into the top-level testbench (uvm/tb/axi_qspi_tb_top.sv) across the external bidirectional SPI pins. This establishes the physical slave endpoint necessary to verify memory-mapped reads, dummy cycles, mode-byte decode, and XIP fast-path transfers. Also resolves host-specific executable paths in theMakefileand documents flash preloading methods in theREADME.md.Related issue or proposal
Related to #1 (Part 1/3: Behavioral Flash Model & Top-Level Hookup)
Design notes
0x03), Fast Read (0x0B), Dual Output Read (0x3B), Quad Output Read (0x6B), and Quad I/O Read (0xEB).0xA0during Quad I/O transactions, allowing subsequent transactions to skip the 8-bit command phase and transition directly to address nibbles.io[3:0]. Keeps lines High-Z during input phases (CMD,ADDR,MODE,DUMMY) and drives read data onnegedge sclkwith proper sampling onposedge sclk.i[7:0] ^ 8'hA5, configurable viaMEM_INIT_FILEparameter ($readmemh) or dynamic runtime taskload_mem_file().Makefiletool definitions (VERILATOR_BIN,UVM_HOME) to remove hardcoded Windows paths, ensuring compatibility with Linux containers and CI environments.Verification
Result: Clean compilation with 0 errors and 0 warnings.
Result: Passed with 0 warnings.
Protocol & Timing Smoke Test:
Ran a cycle-accurate self-checking simulation verifying:
0x03) at0x000000(received0xA5)0x0B) with 8 dummy clocks at0x000004(received0xA1)0xEB) with 4 dummy clocks + Mode0xA0at0x000010(received0xB5)0x000020(received0x85)Result:
>>> ALL 4 FLASH PROTOCOL SMOKE TESTS PASSED! <<<Checklist