[None][test] Add Helix zero-KV multi-GPU regression coverage - #18995
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Included review availability: Your plan provides up to 12 included reviews per hour; 11 remain after this review. WalkthroughThe native Helix all-to-all operator now validates zero-KV mask placement. New tests cover invalid masks, multi-GPU eager execution, CUDA-graph replay, reference accuracy, and unmasked behavior. ChangesZero-KV mask validation and regression coverage
Priority: ⬇️ Low Estimated code review effort: 3 (Moderate) | ~25 minutes Change: Refactor Merge Risk: ⚪ Minimal · up to The bounded barrier reports stalled ranks before CI times out, and cross-device masks are rejected safely. No actionable merge risk remains. 🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
Full details: Docstring CoverageExplanation Docstring coverage is 75.00% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 28 functions across 8 files. (1 skipped: 1 unsupported.)
✨ Finishing Touches🧪 Generate unit tests (beta)
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In `@cpp/tensorrt_llm/thop/alltoallOp.cpp`:
- Around line 237-241: Extend the tests near test_helix_zero_kv.py with
parameterized invalid-mask cases for alltoall_native covering CPU,
non-contiguous, non-bool dtype, empty, and non-divisor masks. Assert each case
is rejected by the expected validation error before kernel execution, while
preserving the existing valid-mask coverage.
- Line 237: Update the validation around CHECK_TH_CUDA(mask) to also require
that mask is on the same CUDA device as partial_o before forwarding
mask.data_ptr() to the Helix kernel. Preserve the existing CUDA validation while
rejecting masks from other CUDA devices.
In `@tests/unittest/_torch/attention/multi_gpu/test_helix_zero_kv.py`:
- Line 167: Replace the unbounded comm.barrier() calls in the multi-GPU test
with the repository’s bounded distributed synchronization helper, preserving
synchronization while ensuring failures surface instead of hanging. If no helper
exists, implement deadline-based polling for a nonblocking MPI barrier and abort
all workers when the deadline expires.
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cpp/tensorrt_llm/kernels/helixAllToAll.cucpp/tensorrt_llm/kernels/helixAllToAll.hcpp/tensorrt_llm/thop/alltoallOp.cpptensorrt_llm/_torch/attention/attention.pytensorrt_llm/_torch/custom_ops/cpp_custom_ops.pytensorrt_llm/_torch/distributed/ops.pytests/unittest/_torch/attention/multi_gpu/test_helix_zero_kv.py
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Stamp on behalf of runtime devs, delegating proper review to @NVIDIA/trt-llm-torch-attention-devs; please ping me if you think this is not accurate
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… alltoall backends A CP rank that owns no KV blocks for a token attends to zero keys, so the attention kernel normalizes by a zero softmax sum and produces NaN. Before the exchange those rows are forced to a no-op contribution (zeroed partial_o, softmax stats of (-inf, 0)) by _helix_sanitize_empty_kv, which materializes a full extra copy of partial_o and softmax_stats on every layer. Fold that fill into work the two backends already do: * MNNVL fifo v2: the all-to-all sender already streams every byte of an entry through shared memory before packing it, so the masked entries are rewritten there, behind a new optional zero_kv_mask argument on trtllm::alltoall_helix_native. The entry is not packed yet, so the overwrite costs no extra global traffic. * NCCL: _helix_sanitize_empty_kv now runs inside the same torch.compile region as the transpose/split that feeds alltoall_helix, so inductor folds the fill into the transposed store instead of writing partial_o and reading it back. fifo v1 keeps calling _helix_sanitize_empty_kv eagerly, and passing zero_kv_mask=None preserves the previous behaviour everywhere, so the sender change is a no-op unless a caller opts in. The outputs are numerically unchanged: the same rows are forced to the same no-op values, just earlier. On GB300 with cp16 the post-process block drops from 10 kernels to 4 and from 28.90 to 16.84 us per layer, with the 16 per-rank ranges non-overlapping ([25.98, 29.81] vs [14.47, 17.47]). The all-to-all kernel itself is unchanged (9.76 -> 9.96 us), confirming the shared-memory rewrite is free. An independent in-process A/B under CUDA graph capture measures -9.71 us per call. Signed-off-by: Xin Guan <294044352+xguannv@users.noreply.github.com>
…ross ranks A CP rank that owns no KV blocks for a token attends to zero keys and hands the combine NaN with a finite sentinel in the softmax stats, so those rows have to be neutralized before the exchange. Nothing exercised that through the exchange: test_helix_postprocess.py calls _helix_sanitize_empty_kv and _helix_zero_kv_mask directly, and test_mla_helix.py gives every rank an equal, non-zero slice of the KV (ctx_len_per_gpu = ctx_len // world_size), so its zero_kv_mask is all False and the neutralization never runs -- on any of the three backends. Add a 2-rank test that drives _helix_post_process with a per-rank mask, poisons the masked rows with NaN, and compares against a float64 reference, for nccl, fifo v1 and fifo v2, plus one CUDA-graph case for fifo v2 since that is how production runs it. A negative control withholds the mask and requires NaN in the output, so a pass means the check can actually fail. Signed-off-by: Xin Guan <294044352+xguannv@users.noreply.github.com>
Three things from review, plus the docstrings the coverage check asked for. alltoall_helix_native only asserted that zero_kv_mask is a CUDA tensor. The kernel dereferences it on partial_o's device, so a mask allocated on a different device passed validation and became an invalid access instead of an error. Require the two to match. Cover every zero_kv_mask validation rule with a test. These run on one GPU: everything the op does before the mask check is host-side shape validation and pointer setup, so an invalid mask raises without a collective and without an initialized MNNVL workspace. They live next to the existing test_helix_postprocess_native_invalid_inputs rather than in the multi-GPU file, which would spend two GPUs on a host-side check. The cross-device case needs a second GPU and is separate. Replace the two comm.barrier() calls that bracket the collective CUDA graph capture with a deadline-bounded Ibarrier. A rank that dies during capture used to leave its peers blocked forever, so the run reported as a hang with no traceback; now it fails and names the rank and the phase. No MPI_Abort: these tests share an MPIPoolExecutor with the rest of the session. Signed-off-by: Xin Guan <294044352+xguannv@users.noreply.github.com>
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Signed-off-by: Xin Guan <294044352+xguannv@users.noreply.github.com>
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Dev Engineer Review
tensorrt_llm/_torch/attention/attention.py.QA Engineer Review
sufficientfor the formatting-only diff.Per-File QA Perspective
tensorrt_llm/_torch/attention/attention.py: Verify that the import-only changes preserve module loading and do not alter runtime behavior.Summary
The original Helix zero-KV optimization from this PR is already present on
mainvia #19273. This PR now contains only the regression coverage and one defensive
boundary check that are still missing:
zero_kv_masklocated on a different CUDA device frompartial_o;No Helix kernel, backend-selection, operator schema, or valid-input behavior is
changed by this PR.
Why this is needed
Existing tests cover zero-KV mask construction and the eager sanitization helper,
but they do not send a mask containing
Truevalues through the cross-rankexchange.
The existing end-to-end Helix tests also give every rank a non-zero KV slice, so
the zero-local-KV neutralization path is not exercised.
The new test poisons masked rows with NaN, drives
_helix_post_processacross tworanks, and compares the output against a float64 reference. An unmasked negative
control verifies that the NaN poison remains observable when sanitization is
disabled, so the positive tests have a meaningful failure signal.
Changes
Defensive validation
alltoall_helix_nativenow requireszero_kv_maskandpartial_oto be on thesame CUDA device.
CHECK_TH_CUDA(mask)only verifies that the mask is a CUDA tensor. Without thesame-device check, a mask allocated on another GPU can pass validation and its
pointer can be dereferenced from the wrong device.
Invalid-input coverage
Adds focused tests for:
Generic CPU, dtype, and non-contiguous validation cases are intentionally omitted
because those contracts are already enforced by the shared validation macros.
Multi-GPU coverage
Adds the following focused 2-rank cases:
The tests retain:
Ibarriercalls around CUDA Graph capture.The bounded barriers turn a failed rank into a traceback instead of leaving the
remaining rank hanging indefinitely.
CI routing
tests/unittest/_torch/attention/multi_gpu/test_helix_zero_kv.pyis explicitlylisted in the pre-merge section of:
tests/integration/test_lists/test-db/l0_dgx_b300.ymlIt maps to:
DGX_B300-4_GPUs-PyTorch-1This explicit entry is required because the directory-level Helix entry is
otherwise only collected by post-merge multi-GPU stages.
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