Skip to content

NRampel/Vending_Machine_Controller

Repository files navigation

VHDL

Vending Machine Controller

Vending Machine FSM Test

A robust Finite State Machine (FSM) implementation of a vending machine controller, designed for FPGA integration

Overview

  • Employs Control Signal Based Design
  • Accepts Multiple Coin Denominations
  • Properly Increments and Decrements
  • Dispenses Desired Item if Correct Amount was Inserted

Key Features:

  • Synchronus Design: All logic is bound to a common clock
  • Input Pulsing & Debouncing: All buttons and switches are debounced to ensure proper calculation
  • 7-Segment Display: Displays machine state and balance, all changes are displayed

Finite State Machine:

graph TD
    S0["S0: Initialize / Clear Credit"]
    S1["S1: Idle / Accept Coins"]
    S2["S2: Refund"]
    S3["S3: Insufficient Funds (Error)"]
    S4["S4: Dispense Item"]

    S0 -->|"Automatic"| S1
    S1 -->|"Quarter / Dollar Added"| S1
    S1 -->|"Refund Button Pressed"| S2
    S1 -->|"Item Selected (Sufficient Credit)"| S4
    S1 -->|"Item Selected (Insufficient Credit)"| S3

    S2 -->|"Timer Complete (ctr = x3FFFFFF)"| S0
    S3 -->|"Timer Complete (ctr = x3FFFFFF)"| S1
    S4 -->|"Timer Complete (ctr = x3FFFFFF)"| S1

Loading

About

A VHDL project that simulates a vending machine on an Artix-7 BASYS3 FPGA Board. Designed on Vivado 2025.2.

Topics

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

 
 
 

Contributors

Languages