Skip to content

Commit e590820

Browse files
committed
如果採用,此提交將修改說明文件
修改項目:
1 parent dc6fa80 commit e590820

1 file changed

Lines changed: 4 additions & 1 deletion

File tree

README.md

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,6 @@
11
Learn VHDL
22
===
3-
使用Altera Cyclone V SoC Kit學習使用FPGA與VHDL的過程檔案。
3+
使用Altera Cyclone V SoC Kit和Altera Cyclone III DE0學習使用FPGA與VHDL的過程檔案。
4+
使用的晶片:
5+
* Altera Cyclone V SoC Kit:5CSXFC6D6F31C8NES
6+
* Altera Cyclone III DE0:EP3C16F484C6N

0 commit comments

Comments
 (0)